A digital phase‐locked loop with and filter

Abstract

In general, it is known that if the stationary characteristics of a PPL, phase‐locked loop, are improved, its transient response characteristics are deteriorated, while if the transient response characteristics are improved, its stationary characteristics are deteriorated. The DPLL, digital PLL, is not an exception in regards to the features. Here, we will realize a loop which is superior both in the effective phase error and the average transient response time compared with conventional DPLL with less deterioration of the average transient response time caused by improved effective phase error, due to inserting AND filter to the conventional binary quantized DPLL. The characteristics of the proposed loop are analyzed theoretically by use of the Markov chain and confirmed to be identical by computer simulation. These results prove that the proposed loop has better characteristics than the conventional ones.

Digital phase-locked loop constructed by AND-filter

“…We analyze the proposed loop with Markov model [2] [4]. We assume that the input frequency fi is equal to the output frequency fo (ft = fo).…”

“…These results are agreed with theoretical values. We choose the parameters with a view to equalizing the noise suppression effects in this proposed loop, loop [3] and loop [4]. The parameters are as follows,…”

“…We compare this proposed loop with the conventional loops[3] [4]. It is found that the phase acquisition speed of this proposed loop is better than that of either the loop[3] or the loop[4] with same noise suppression effect.…”

“…In this loop, RWF in conventional loop [3] is replaced by JND-filter. Therefore, the structure of this loop is very simple, We compare this proposed loop with the conventional loop [3] and the DPLL inserted AND-filter [4]. And the phase acquisition speed of this proposed loop is better than that of either the loop[f] or the loop [4] on the condition of same noise suppression effect.…”

“…Then it is difficult to make phase acquisition speed faster with good noise suppression. Then, we propose a new type of DPLL with AND-filter [4] instead of RWF, for the purpose of having the faster phase acquisition speed. In this loop, RWF in conventional loop [3] is replaced by JND-filter.…”