A Digital-Summing Feedforward Σ-Δ Modulator and its Application to a Cascade ADC

Tang, Yi; Sk, Gupta; Paramesh, Jeyanandh; Allstot, D.J.

doi:10.1109/iscas.2007.378569

Cited by 9 publications

(3 citation statements)

References 4 publications

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“…With the popularity of the full feedforward delta-sigma topology [8][9][10][11], the summation circuit has become an important component of multi-bit DSM. Conventional summation circuits use active operational transconductance amplifiers (OTAs) as the core to sum up the signals at each node of the circuit, consuming a large amount of active power [12][13][14][15]. In order to reduce this part of power consumption, passive summation schemes have been widely adopted.…”

Section: Introductionmentioning

confidence: 99%

Low-power Multi-bit Delta-Sigma Modulator based on Passive and Attenuationless Summation Scheme

Wei,

Huang,

Huang

et al. 2023

Preprint

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In the field of delta-sigma modulators, reducing system power consumption without sacrificing accuracy has become a challenge. The summing circuit, as the main part of the cascade-of-integrator-in-feedforward delta-sigma modulator, consumes a significant amount of power in active summing. On the other hand, passive summing circuits have low power consumption but can cause attenuation in the summing results. This article proposes a low-power multi-bit delta-sigma modulator based on passive and attenuationless summation scheme. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through bidirectional sampling technique, compensating for the inherent attenuation caused by passive summation, thus eliminating the need for active OTA to achieve perfect summation. A 2-order delta-sigma modulator based on 4-bit 1-order passive noise-shaping (NS) SAR quantizer is designed to verify the scheme. By combining a passive NS SAR as the 4-bit quantizer and the third-stage integrator of the system, and incorporating an energy-efficient cascode floating inverter amplifier (FIA) structure as the core active OTA, these elements have significantly enhanced the energy-efficiency of the modulator. Simulation results show that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and Schreier figure-of-merit (FoM) of SNDR is 183.92 dB.

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Section: Introductionmentioning

confidence: 99%

Low-power Multi-bit Delta-Sigma Modulator based on Passive and Attenuationless Summation Scheme

Wei,

Huang,

Huang

et al. 2023

Preprint

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“…A method employing a SC summing op-amp to add the three feedforward signals induces a large output swing of the summing block. This method increases the ADC power consumption and presents stringent headroom requirements for summing op-amp [2]. Also, a large input swing demands more current consumption for quantizer, because the available input range of a differential pair is approximately proportional to I SS /g m .…”

mentioning

confidence: 99%

“…Other methods such as digital summing technique [2] or by combining the summing function with the second-stage integrator [4] make design complex and are somehow affected by the limitations described above. In this work, we try to develop a simple but efficient way to implement the summing function with high accuracy.…”

mentioning

confidence: 99%

A novel approach to implement summing function for feedforward .DELTA.-.SIGMA. AD modulator

Wang

Ido

Matsuoka

et al. 2008

IEICE Electron. Express

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Abstract:A novel approach is proposed to implement summing function for feedforward Δ-Σ modulator. Unlike the conventional methods, neither summing op-amp nor a large number of summing capacitors are used in our design. The high-accuracy summing function is accomplished by using a few capacitors with small size to compensate the summing error caused by parasitic capacitance, thereby resulting in a smaller chip area and no additional power dissipation. Keywords: summing function, feedforward, Δ-Σ modulator Classification: Integrated circuits power Sigma-Delta modulator for broadband Analog-to-Digital conversion," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1855-1864, Sept. 2005

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Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme

Wei,

Huang,

Huang

et al. 2024

Circuit Theory & Apps

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A low‐power multibit delta–sigma modulator (DSM) based on a passive and unattenuated summation scheme is proposed. The summation circuit achieves multiplication of the voltage signal carried on the summation capacitor through a bidirectional sampling technique, thereby compensating for the inherent attenuation caused by passive summation, which eliminates the need for an active operational transconductance amplifier (OTA) to achieve perfect summation. Here, a second‐order DSM based on a 4‐bit first‐order passive noise‐shaping (NS) SAR quantizer is employed to satisfy the SNDR requirements exceeding 100 dB, which validates the reliability of the summation scheme. In addition, a cascoded floating inverter amplifier (FIA) is used as the core OTA to further improve system energy efficiency. Simulation results demonstrate that at a supply voltage of 1.2 V and a bandwidth of 20 kHz, the SNDR reaches 102.62 dB, power consumption is only 148.32 μW, and the Schreier figure‐of‐merit (FoM) of the SNDR is 183.92 dB. The results demonstrate that the proposed DSM has considerable potential for widespread application in the audio domain.

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A Digital-Summing Feedforward Σ-Δ Modulator and its Application to a Cascade ADC

Cited by 9 publications

References 4 publications

Low-power Multi-bit Delta-Sigma Modulator based on Passive and Attenuationless Summation Scheme

Low-power Multi-bit Delta-Sigma Modulator based on Passive and Attenuationless Summation Scheme

A novel approach to implement summing function for feedforward .DELTA.-.SIGMA. AD modulator

Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme

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