A disturb-free subthreshold 9T SRAM cell with improved performance and variation tolerance

Lu, Chien-Yu; Chuang, Ching-Te

doi:10.1109/socc.2013.6749710

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Cited by 5 publications

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“…To improve the performance and data stability, several structures [3,4,5] have been proposed at the cell level. For instance, a new 7T cell is proposed in [3], which improves the stability of the SRAM cell and reduces the average power dissipation during the read write operation and reduces the leakage power in standby mode.…”

Section: Introductionmentioning

confidence: 99%

A Novel 8T SRAM Cell with Improved Read and Write Margins

Li¹,

Lin²,

Zhang³

et al. 2015

Proceedings of the 2015 International Conference on Applied Science and Engineering Innovation

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A highly stable 8T SRAM cell is presented to improve the Static Noise Margin (SNM). The proposed 8T SRAM cell uses a single-bit line structure to perform read and write operation. The design enhances the write ability by breaking-up the feedback loop of the inverter pair. It also improves the read stability by eliminating the effects from the bit-line. The simulations show that the proposed 8T cell offers 2.07x read static noise margin, 1.41x and 2.60x in write '0' margin compared to the conventional 6T cell and 7T cell, respectively. Besides, the proposed structure has a significant improvement in writing '1' operation and HSNM.

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