A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator

Abstract

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-m process technology. It has an area of 0.035 mm and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.Index Terms-DLL, dual edge triggered, jitter, lock speed, loop stability.

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

“…2. To enhance the lock time, which is an important design parameter in the clock generator, a dual-edge-triggered phase-detector-based DLL core [14] is adopted. Similar to previous frequency multipliers, the proposed frequency multiplier is also composed of a pulse generator, a multiplication-ratio control logic, and an edge combiner.…”

“…Fig. 3 shows the operations of the DLL in [14] and the proposed frequency multiplier. The dual-edge-triggered phase-detector compares both the positive and the negative edges of CLK REF,DCK and CLK OUT,DCK , which are the dutycycle recovered clocks of CLK REF and CLK OUT using the duty-cycle keeper.…”

Delay-Lock-Loop-Based Inductorless and Electrolytic Capacitorless Pseudo-Sine-Current Controller in LED Lighting Systems

“…THD and HF can be obtained in (22) and (23), respectively, from the calculation result of (21) In order to find the optimal design in PSC, the indexes of performance are shown in Fig. 7 according to the above derivations.…”

“…12(a), the signal CLK is injected to the DLL circuit [22], [23] to adjust the duration of each turn-ON period of the LED subset for high accuracy brightness control. Phase detector (PD) can compare the phase difference between the reference clock, CLK, and the output clock CLK o to generate the control signals, UP and DN.…”

Dual Phase Detector Based Delay Locked Loop for High Speed Applications

“…Non-ideal blocks and also mismatches in DLL result in jitter at the output of them. One of the main sources of jitter in DLLs is PFD [8]. Recent works try to decrease the phase offset in PFDs [9][10][11] by reducing the reset path delay [10,11] or dead zone [9] in PFD to have better jitter performance.…”