A Domain-Specific On-Chip Network Design for Large Scale Cache Systems

Yan, Jin; Kim, Eim Jung; Yum, Ki Hwan

doi:10.1109/hpca.2007.346209

Cited by 26 publications

(18 citation statements)

References 20 publications

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“…Jin et al [20] propose a halo network that best meets the needs of a single-core D-NUCA cache, where requests begin at a cache controller and radiate away as they perform the search. Beckmann and Wood [6] propose the use of transmission lines to support low-latency access to distant cache banks.…”

Section: Background and Related Workmentioning

confidence: 99%

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Madan

Zhao

Muralimanohar

et al. 2009

2009 IEEE 15th International Symposium on High Performance Computer Architecture

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Section: Background and Related Workmentioning

confidence: 99%

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Madan

Zhao

Muralimanohar

et al. 2009

2009 IEEE 15th International Symposium on High Performance Computer Architecture

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“…They advocate using private L2 caches due to the high area overhead required for shared L2s. Muralimanohar et al [2008] and Jin et al [2007] consider interconnect design for large on-chip caches and introduce interconnect enhancements that significantly reduce their overall access latency.…”

Section: Related Workmentioning

confidence: 99%

An analysis of on-chip interconnection networks for large-scale chip multiprocessors

Sánchez

Kozyrakis

2010

ACM Trans. Archit. Code Optim.

100

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With the number of cores of chip multiprocessors (CMPs) rapidly growing as technology scales down, connecting the different components of a CMP in a scalable and efficient way becomes increasingly challenging. In this article, we explore the architectural-level implications of interconnection network design for CMPs with up to 128 fine-grain multithreaded cores. We evaluate and compare different network topologies using accurate simulation of the full chip, including the memory hierarchy and interconnect, and using a diverse set of scientific and engineering workloads.We find that the interconnect has a large impact on performance, as it is responsible for 60% to 75% of the miss latency. Latency, and not bandwidth, is the primary performance constraint, since, even with many threads per core and workloads with high miss rates, networks with enough bandwidth can be efficiently implemented for the system scales we consider. From the topologies we study, the flattened butterfly consistently outperforms the mesh and fat tree on all workloads, leading to performance advantages of up to 22%. We also show that considering interconnect and memory hierarchy together when designing large-scale CMPs is crucial, and neglecting either of the two can lead to incorrect conclusions. Finally, the effect of the interconnect on overall performance becomes more important as the number of cores increases, making interconnection choices especially critical when scaling up.

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“…In a network-based interconnect, the line can be sought using multiple unicast messages [10]. Alternatively, the interconnect designer may add some extra logic within the network infrastructure to facilitate an inband deadlock-free broadcast service (e.g., [11]). The BENoC architecture takes this approach one step further and offers a more efficient alternative, by using the bus to broadcast the query to all cache banks.…”

Section: Benoc For Cmp Dnucamentioning

confidence: 99%

BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

Walter

Cidon

Kolodny

2008

IEEE Comput. Arch. Lett.

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Abstract-Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future chip multi-processor (CMP). However, while NoCs are very efficient for delivering high throughput point-to-point data from sources to destinations, their multi-hop operation is too slow for latency sensitive signals. In addition, current NoCS are inefficient for broadcast operations and centralized control of CMP resources. Consequently, state-of-the-art NoCs may not facilitate the needs of future CMP systems. In this paper, the benefit of adding a low latency, customized shared bus as an internal part of the NoC architecture is explored. BENoC (Bus-Enhanced Network on-Chip) possesses two main advantages: First, the bus is inherently capable of performing broadcast transmission in an efficient manner. Second, the bus has lower and more predictable propagation latency. In order to demonstrate the potential benefit of the proposed architecture, an analytical comparison of the power saving in BENoC versus a standard NoC providing similar services is presented. Then, simulation is used to evaluate BENoC in a dynamic non-uniform cache access (DNUCA) multiprocessor system.

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A Domain-Specific On-Chip Network Design for Large Scale Cache Systems

Cited by 26 publications

References 20 publications

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy

An analysis of on-chip interconnection networks for large-scale chip multiprocessors

BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

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