BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

Walter, Isask'har; Cidon, Israel; Kolodny, Avinoam

doi:10.1109/l-ca.2008.11

Cited by 11 publications

(7 citation statements)

References 15 publications

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“…This paper, however, does not address the problem of gathering multiple acknowledgements with the same destination node. Walter et al [14] explore the benefits of adding a low‐latency, customised shared bus as an integral part of the NoC architecture. The bus is used for some transactions such as broadcast of queries, fast delivery of control signals and quick exchange of small data items.…”

Section: Related Workmentioning

confidence: 99%

Built‐in fast gather control network for efficient support of coherence protocols

Lodde

Roca

Flich

2013

IET Computers & Digital Techniques

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Future chip multiprocessors will include hundreds of cores organised in a tile-based design pattern. These systems commonly employ a shared memory programming model, thus needing a coherence protocol to keep data consistent on the various levels of the cache hierarchy. Usually an invalidation-based protocol is used, where shared copies are invalidated before a write operation. In this study, the authors propose a NoC re-organisation in which a small and fast dedicated control network is used to transmit acknowledgement messages related to the invalidation process, thus relieving the NoC from a considerable percentage of traffic. The dedicated control network is evaluated both with full map directories and with a broadcast-based protocol (Hammer). Experimental evaluation shows significant gains in performance. With a low area overhead (<2.5%), the control network reduces NoC traffic and miss latency, thus reducing execution time up to 16%. Simulation results show a reduction of network traffic up to 80% and a reduction of store and load miss latency up to 70 and 40%, respectively.

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Section: Related Workmentioning

confidence: 99%

Built‐in fast gather control network for efficient support of coherence protocols

Lodde

Roca

Flich

2013

IET Computers & Digital Techniques

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“…More recently, Walter et al [20] explore the benefits of adding a low-latency, customized shared bus as an integral part of the NoC architecture. This bus is used for certain transactions such as broadcast of queries, fast delivery of control signals, and quick exchange of small data items.…”

Section: Related Workmentioning

confidence: 99%

Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs

Flores

Aragón

Acacio

2010

IEEE Trans. Comput.

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Abstract-Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processing cores on the same chip. Chip multiprocessors (CMPs) constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and the increasing transistor density have revealed power dissipation and temperature as critical design issues in current and future architectures. Previous studies have shown that the interconnection network of a Chip Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics. In this work, we show how messages can be efficiently managed, from the point of view of both performance and energy, in tiled CMPs using a heterogeneous interconnect. Our proposal consists of two approaches. The first is Reply Partitioning, a technique that splits replies with data into a short Partial Reply message that carries a subblock of the cache line that includes the word requested by the processor plus an Ordinary Reply with the full cache line. This technique allows all messages used to ensure coherence between the L1 caches of a CMP to be classified into two groups: critical and short, and noncritical and long. The second approach is the use of a heterogeneous interconnection network composed of low-latency wires for critical messages and low-energy wires for noncritical ones. Detailed simulations of 8 and 16-core CMPs show that our proposal obtains average savings of 7 percent in execution time and 70 percent in the Energy-Delay squared Product (ED 2 P ) metric of the interconnect over previous works (from 24 to 30 percent average ED 2 P improvement for the full CMP). Additionally, the sensitivity analysis shows that although the execution time is minimized for subblocks of 16 bytes, the best choice from the point of view of the ED 2 P metric is the 4-byte subblock configuration with an additional improvement of 2 percent over the 16-byte one for the ED 2 P metric of the full CMP.Index Terms-Tiled chip multiprocessor, energy-efficient architectures, cache coherence protocol, heterogeneous on-chip interconnection network, parallel scientific applications.

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“…However, the all-to-all operation is not addressed. Recently, Walter et al [29] explore the benefits of adding a low-latency, customized shared bus as an integral part of the NoC architectures. This bus is used for certain transactions such as broadcast of queries, fast delivery of control signals, and quick exchange of small data items (one-to-all operation).…”

Section: Introductionmentioning

confidence: 99%

All-To-All Broadcast in Hexagonal Torus Networks On-Chip

Touzene

2015

IEEE Trans. Parallel Distrib. Syst.

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Hexagonal torus networks are special family of Eisenstein-Jacobi (EJ) Networks which have gained popularity as good candidates network On-Chip (NoC) for interconnecting Multiprocessor System-on-Chips (MPSoCs). They showed better topological properties compared to the 2D torus networks with the same number of nodes. All-to-all broadcast is a collective communication algorithm used frequently in some parallel applications. Recently, an off-chip all-to-all broadcast algorithm has been proposed for hexagonal torus networks assuming half-duplex links and all-ports communication. The proposed all-to-all broadcast algorithm does not achieve the minimum transmission time and requires 24k extra buffers, where k is the network diameter. We first extend this work by proposing an efficient all-to-all broadcast on hexagonal torus networks under full-duplex links and all-ports communications assumptions which achieves the minimum transmission delay but requires 36k extra buffers per router. In a second stage, we develop a new all-to-all broadcast more suitable for hexagonal torus network on-chip that achieves optimal transmission delay time without requiring any extra buffers per router. By reducing the amount of buffer space, the new all-to-all broadcast reduces the routers cost which is an important issue in NoCs architectures.

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BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

Cited by 11 publications

References 15 publications

Built‐in fast gather control network for efficient support of coherence protocols

Built‐in fast gather control network for efficient support of coherence protocols

Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs

All-To-All Broadcast in Hexagonal Torus Networks On-Chip

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