Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs

Abstract

Abstract-Continuous improvements in integration scale have made major microprocessor vendors to move to designs that integrate several processing cores on the same chip. Chip multiprocessors (CMPs) constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and the increasing transistor density have revealed power dissipation and temperature as critical design issues in current and future architectures. Previous studies have shown that the interconnection network of a Chip Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics. In this work, we show how messages can be efficiently managed, from the point of view of both performance and energy, in tiled CMPs using a heterogeneous interconnect. Our proposal consists of two approaches. The first is Reply Partitioning, a technique that splits replies with data into a short Partial Reply message that carries a subblock of the cache line that includes the word requested by the processor plus an Ordinary Reply with the full cache line. This technique allows all messages used to ensure coherence between the L1 caches of a CMP to be classified into two groups: critical and short, and noncritical and long. The second approach is the use of a heterogeneous interconnection network composed of low-latency wires for critical messages and low-energy wires for noncritical ones. Detailed simulations of 8 and 16-core CMPs show that our proposal obtains average savings of 7 percent in execution time and 70 percent in the Energy-Delay squared Product (ED 2 P ) metric of the interconnect over previous works (from 24 to 30 percent average ED 2 P improvement for the full CMP). Additionally, the sensitivity analysis shows that although the execution time is minimized for subblocks of 16 bytes, the best choice from the point of view of the ED 2 P metric is the 4-byte subblock configuration with an additional improvement of 2 percent over the 16-byte one for the ED 2 P metric of the full CMP.Index Terms-Tiled chip multiprocessor, energy-efficient architectures, cache coherence protocol, heterogeneous on-chip interconnection network, parallel scientific applications.

Tree-Mesh Heterogeneous Topology for Low-Latency NoC

“…Dejavu switching [20] has similar idea, but it utilizes circuit-switching and packet-switching together in a multi-plane NoC to separate control and data packets. Also, [21] exploits heterogeneous wires to transfer critical packets on low-latency wires. [22] claims that using multiple mesh network of different configuration can be beneficial.…”

Ordering circuit establishment in multiplane NoCs

“…When reducing the speed of the data plane to 2.66GHz in a split packet switch (PS 4/2.66) the performance reduces considerably. We also tried to send the critical word on the faster control plane (PS+CW 4/2.66) [Flores et al 2010] which provides a slight benefit but does not approach the speed of the baseline. Finally, our proposed Déjà Vu switched network (DV 4/2.66) restores the performance of the baseline and is comparable with PS 4/4, while providing the energy reductions of reducing the data plane speed as enumerated in Figure 15(b).…”

“…With 75-byte baseline links, the authors report a reduction in both execution time and energy consumption, however, they report significant performance losses with narrower links. Flores et al [2010] also propose a heterogeneous interconnect for a 2D mesh topology in which the baseline NoC is replaced with one having two sets of wires; one 2× faster and the other 2× slower than the baseline. The authors report results with similar trends to the results in Cheng et al [2006].…”

Dapsco

“…Regarding NoCs, cache coherence protocols can take advantage of heterogeneous networks to reduce power consumption by transmitting critical, short messages through fast power-consuming wires and non-critical messages through slower low-power wires [Flores et al 2010]. As for cache architecture, TurboTag [Lotfi-Kamran et al 2010] uses bloom filters to avoid unnecessary tag lookups and reduce power consumption.…”