A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory

Yilmaz, Yalcin; Mazumder, Pinaki

doi:10.1109/tnano.2017.2741504

Cited by 30 publications

(14 citation statements)

References 40 publications

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“…Table III compares the hardware requirements and speed of the proposed sensing scheme (with MOS capacitor) with conventional schemes. Parallel sensing scheme of [19] requires 1M Ω resistors which will be difficult to fabricate in CMOS. In contrast, the circuit of Fig.…”

Section: Significance Of Resultsmentioning

confidence: 99%

“…In contrast, the circuit of Fig. 3 does not have any passive element and will occupy less area than the sensing circuit of [19]. Further, our sensor scales well from 2-bit to 3-bit MLC by requiring only one additional flip-flop and logic gate (for 3-bit counter).…”

Section: Significance Of Resultsmentioning

confidence: 99%

“…Further, our sensor scales well from 2-bit to 3-bit MLC by requiring only one additional flip-flop and logic gate (for 3-bit counter). The serial approach will require 7 I REF [20], while the parallel approach will require 7 op-amps and resistors [19] to sense 3-bits/cell.…”

Section: Significance Of Resultsmentioning

confidence: 99%

See 2 more Smart Citations

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Reuben

Fey

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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The quest to increase memory density in Resistive Random Access Memory (RRAM) has motivated researchers to store more bits/cell by implementing Multi-Level Cell (MLC) or multi-bit RRAM. Implementing multiple states narrows the distance between states, making sensing of MLC RRAM a challenging task. In this paper, we present a circuit which senses the state of a MLC by converting the current drawn from the cell to voltage pulses, where the number of pulses is proportional to the current's magnitude. The circuit distinguishes between the states by the relative current's magnitude and hence does not require an absolute reference. Simulations in IHP's 130 nm CMOS technology confirmed fast (single step) sensing while tolerating appropriate variations in the sensed resistance. The proposed circuit is also area efficient when compared to conventional parallel sensing approach.

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Section: Significance Of Resultsmentioning

confidence: 99%

Section: Significance Of Resultsmentioning

confidence: 99%

See 1 more Smart Citation

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Reuben

Fey

2019

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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“…One of the most promising approaches in this field is hybrid Nano/CMOS technology. This is due to the unique characteristics of Memristors such as being capable of scaling to Nano-metric sizes [5][6][7][8][9] and having a very fast response time [10].…”

Section: Introductionmentioning

confidence: 99%

“…A diversity of Memristor devices based on resistance switching property exist, which use different materials and algorithms [7][8][9]. The Memristors arrays are used in a variety of today's electronic circuits [10][11][12][13][14][15][16][17][18][19][20][21]. In [16], an algorithm called material implication (IMP) was provided that can be used for many different Boolean logic functions.…”

Section: Introductionmentioning

confidence: 99%

Novel design for Memristor‐based n to 1 multiplexer using new IMPLY logic approach

Karimi

Rezai

2019

IET Circuits, Devices & Systems

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Multiplexer is one of the widely used logics in VLSI design. This paper presents a novel method to design the n-input Memristor-based AND and OR operations. Then, two methods are proposed to design complete and incomplete n to 1 Memristor-based multiplexers (MUXs) based on these novel Memristor-based AND and OR operations. The simulation results confirm the accuracy and functionality of the proposed methods. The comparison between n to 1 MUXs shows that the proposed n to 1 MUXs provide improvements in terms of area and speed compared to other n to 1 MUXs.

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Memristor‐based 2D1M architecture: Solution to sneak paths in multilevel memory

Ravi

Singh

Reka

2020

Trans Emerging Tel Tech

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The memristor, the fourth fundamental elements have shown the potential to revolutionize the present storage, analog, and digital computational technologies. The ability to remember its previous state in the absence of any stimuli has made the memristor as a prime candidate for nonvolatile memory. However, the sneak path is one of the main problems hampering the implementation of memristor‐based crossbar memories. In this article, we introduce a new crossbar architecture that is capable of storing multibit per cell and eliminates the sneak paths without adding any complex circuitry. The approximate write delay of the proposed memory cell is 20 mS which is very close to the delay of the single bit cell. The proposed architecture was validated by storing four different logic states in each cell of the 4 × 4 memory. Hence, one memory cell of the proposed architecture replaces four cells of the single‐bit memory at the cost of one additional diode per cell. Therefore, the proposed scheme saves considerable area when compared with the conventional single‐bit memory array. The write/read operations are validated by a generic, accurate, and efficient “voltage threshold adaptive memristor” (VTEAM) model. The simulation results prove that the proposed circuitry can read the memory content even after 2000 cycles without any sneak paths problem.

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A Drift-Tolerant Read/Write Scheme for Multilevel Memristor Memory

Cited by 30 publications

References 40 publications

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

A Time-based Sensing Scheme for Multi-level Cell (MLC) Resistive RAM

Novel design for Memristor‐based n to 1 multiplexer using new IMPLY logic approach

Memristor‐based 2D1M architecture: Solution to sneak paths in multilevel memory

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