A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

Rusu, Stefan; Tam, Simon; Muljono, H.; Ayers, D.; Chang, J.

doi:10.1109/isscc.2006.1696062

Cited by 59 publications

(42 citation statements)

References 2 publications

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“…We assume idle memory cells are resilient to common-mode voltage fluctuations, which affect both sides of a differential SRAM cell equally. Recent cache designs from Intel [23] demonstrate that memory cells retain state in lower-voltage drowsy modes, where the voltages are much lower than the low-end voltage-emergency level we assume. Furthermore, we assume idle memory cells can have additional protection by using standard ECC measures common in today's microprocessors.…”

Section: Rb-protected and Tm-protected Zonesmentioning

confidence: 86%

DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors

Gupta

Rangan

Smith

et al. 2008

2008 IEEE 14th International Symposium on High Performance Computer Architecture

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Increases in peak current draw and reductions in the operating voltage of processors stress the importance of dealing with voltage fluctuations in processors. Noise-margin violations lead to undesired effects, like timing violations, which may result in incorrect execution of applications. Several recent architectural solutions for inductive noise have been proposed that, unfortunately, have a strong correlation to the underlying power-delivery package model and require a feedback loop that is largely constrained by the voltage/current sensor characteristics. The resulting solutions are not robust across a wide range of microprocessor designs and packaging technologies. This paper proposes a DelayedCommit and Rollback scheme (DeCoR) that guarantees correctness, insensitive to the package model or the responsiveness of the voltage sensors. In particular, our approach recovers from, rather than attempting to avoid, voltage emergencies. This approach incurs a small performance penalty when compared to an ideal machine that does not have voltage emergencies. We show that explicit checkpoint-recovery schemes, intended to handle infrequent events, e.g., radiation-induced soft errors, suffer from large performance overheads for frequently-occurring voltage emergencies. DeCoR requires very few modifications to modern processor designs, as it leverages the existing store queue and reorder buffers. Unlike conventional designs that conservatively protect all components of the processor from inductive noise with overly-large timing margins, our approach only requires conservative protection of the architected register state and cache write paths.

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Section: Rb-protected and Tm-protected Zonesmentioning

confidence: 86%

DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors

Gupta

Rangan

Smith

et al. 2008

2008 IEEE 14th International Symposium on High Performance Computer Architecture

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“…We assume the power consumption of the baseline OoO core to be equal to Xeon's nominal operating power [27]. Idle power is estimated to be 30% of the nominal power [20].…”

Section: Additional Detailsmentioning

confidence: 99%

Meet the walkers

Kocberber¹,

Grot

Picorel³

et al. 2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

151

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The explosive growth in digital data and its growing role in real-time decision support motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance and ushered an era of power-limited chips. These developments motivate the design of DBMS accelerators that (a) maximize utility by accelerating the dominant operations, and (b) provide flexibility in the choice of DBMS, data layout, and data types.We study data analytics workloads on contemporary inmemory databases and find hash index lookups to be the largest single contributor to the overall execution time. The critical path in hash index lookups consists of ALU-intensive key hashing followed by pointer chasing through a node list. Based on these observations, we introduce Widx, an on-chip accelerator for database hash index lookups, which achieves both high performance and flexibility by (1) decoupling key hashing from the list traversal, and (2) processing multiple keys in parallel on a set of programmable walker units. Widx reduces design cost and complexity through its tight integration with a conventional core, thus eliminating the need for a dedicated TLB and cache. An evaluation of Widx on a set of modern data analytics workloads (TPC-H, TPC-DS) using full-system simulation shows an average speedup of 3.1x over an aggressive OoO core on bulk hash table operations, while reducing the OoO core energy by 83%.

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“…This is applied to the majority of devices in this chapter since Long-L transistors (i.e. nominal + 10%) have less leakage [30]. As shown in the voltage transfer curve (VTC) of Fig.…”

Section: Invertermentioning

confidence: 99%

“…4.3 were sized as Long-L transistors (i.e. nominal + 10%) since long-L transistors [30] have 3x lower leakage. HVT was chosen for most transistors since it results in at least an order of magnitude decrease in leakage current per µm of NMOS (or PMOS) width.…”

Section: Leakagementioning

confidence: 99%

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Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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Ajoitusvirheentunnistus (TED) mahdollistaa energian kulutuksen vähentämisen mikroprosessoreissa. Tässä diplomityössä on kaksi versiota ajoitusvirheentunnistavasta salvasta (esim. TDTBsubI ja TDTBsubII) ja systeemitason testipiiri (SystemTest), joka käyttää TDTBsub salpaa, mikä on suunniteltu toimimaan kynnysalueen alapuolella. Diplomityö esittelee ensin dynaamisen jännitteen skaalauksen (DVS), koska TED käytetään sellaisissa järjestelmissä. Seuraavaksi esitellään teoriaa kynnysalueen alapuolen suunnittelun haasteista. Sitten esitellään molempien TDTBsub salpojen ja SystemTest-lohkojen suunnittelu. Simulaatiotuloksia esitellään keskittyen operaatiotaajuuteen, energian kulutukseen ja toimintavarmuuteen variaatiot huomioon ottaen. Operoitaessa kynnysalueen alapuolella TDTB-piirillä keskityttiin koon mitoittamiseen ja suunnittelutyyliin. Ennen kaikkea kaikkien komponenttien mitoituksen piti olla suurempi kuin minimi CMOS-tekniikan leveydet. Vaikka mitoittamisella saavutettiin toimintavarmuutta kynnysalueen alapuolella toimittaessa myös energian kulutus kasvoi siellä toimittaessa. Perinteisiä vuotovirtojen vähentäviä mitoitustoimenpiteitä tehtiin suurimmalle osalle komponenteista. Logiikkatyyli on tärkeää kynnysalueen alapuolella operoitaessa. TDTBsubII salvassa uuden tekniikan näytetään antavan systeemitason suorituskykyä. Simulaatioilla näytettiin kuinka ajoitusvirheentunnistus kykeni toimimaan kynnystason alapuolella. TDTBsubI:n ja yhteenlaskun testipiirin piirinkuvio tehtiin 65nm CMOS-prosessilla. TDTBsubII salpaa ei tehty, koska se suunniteltiin piirin määräajan jälkeen. Piiriä tarkasteltaessa osoittautui, että piiri ei toiminut. Piirin toimimattomuus johtui tuotantovaiheessa tapahtuneesta virheestä eikä suunnittelusta. Avainsanat:sub-threshold,weak inversion,low power,low voltage,digital CMOS To operate TDTBsub into sub-threshold, attention was given to sizing and logic style. In general, the sizing of all components was required to be larger than the minimum CMOS width. Although this provided robustness in sub-threshold, the energy consumption in above sub-threshold was much higher. General leakage reduction sizing techniques were also applied to the majority of components. The choice of logic style is important for sub-threshold operation. In the TDTBsubII latch, a new technique is shown to provide system-level capability. Simulations displayed the capability of TED in sub-threshold. The layout of TDTBsubI and an adder test circuit were constructed in 65 nm CMOS. The TDTBsubII latch was not built since it was designed after the chip deadline. Upon inspection of the chip, it was determined to be inoperative. This mistake was a result of the manufacturering process and not the design in this work. Keywords:sub-threshold, weak inversion, low power, low voltage, digital CMOS ii ForewordThe work for this thesis was carried out at the Electronic Circuit Design Laboratory (ECDL) of TKK. The financial support of this project was provided by the Academy of Finland. The project was coordinated with University of Turku ...

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A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

Cited by 59 publications

References 2 publications

DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors

DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors

Meet the walkers

Sub-threshold operation of a timing error detection latch

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