A Family of 32 nm IA Processors

Kurd, Nasser; Bhamidipati, Subramani; Mozak, Chris; Miller, Jeffrey L.; Mosalikanti, Praveen; Wilson, Timothy M.; El-Husseini, Ali M; Neidengard, Mark; Aly, R.E.; Nemani, Mahadev; Chowdhury, Muntaquim; Kumar, Rajesh

doi:10.1109/jssc.2010.2079430

Cited by 25 publications

(1 citation statement)

References 3 publications

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“…This is the reason why its access time is very fast and it is used as register files and cache memories in microprocessors, etc. 1,2) However, since it consumes static power during data hold, the standby power becomes larger and larger when its threshold voltages of the metal-oxidesemiconductor field-effect transistors (MOSFETs) are reduced as the operating voltage gets smaller. 3) In addition to that, the static noise margin (SNM) of the SRAM cells is also reduced as the feature size shrinks.…”

Section: Introductionmentioning

confidence: 99%

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Ohsawa

Iga

Ikeda

et al. 2012

Jpn. J. Appl. Phys.

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A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).

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Section: Introductionmentioning

confidence: 99%

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Ohsawa

Iga

Ikeda

et al. 2012

Jpn. J. Appl. Phys.

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Variation-Mitigation for Reliable, Dependable and Energy-Efficient Future System Design

Das

2017

Dependable Multicore Architectures at Nanoscale

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Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits

Jiao

Kursun

2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Multi-threshold CMOS (MTCMOS) is the most widely used circuit technique for suppressing subthreshold leakage currents in idle circuits. When a conventional MTCMOS circuit transitions from SLEEP mode to ACTIVE mode, voltages of power and ground distribution networks are disturbed. Mode transition noise phenomenon in MTCMOS circuits is examined in this chapter. An MTCMOS circuit technique with three operating modes (tri-mode) is described for noise suppression during activation events. A threshold voltage tuning methodology is presented to further alleviate the mode transition noise with smaller sleep transistors in MTCMOS circuits. Alternative applications of tri-mode MTCMOS for data preservation and leakage power reduction in idle memory elements are also discussed.

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A Family of 32 nm IA Processors

Cited by 25 publications

References 3 publications

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction

Variation-Mitigation for Reliable, Dependable and Energy-Efficient Future System Design

Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits

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