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Net assignment for the FPGA-based logic emulation system in the folded-clos network structure," IEEE Trans. Computer-Aided Design, vol. 16, pp. 316-320, Mar. 1997. [9] Analysis of Buck Converters for On-Chip Integration With a Dual Supply Voltage MicroprocessorVolkan Kursun, Siva G. Narendra, Vivek K. De, and Eby G. FriedmanAbstract-An analysis of an on-chip buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4% at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2-0.9 volts while supplying 9.5 A average current. The area occupied by the buck converter is 12.6 mm assuming an 80-nm CMOS technology. An estimate of the efficiency is shown to be within 2.4% of simulation at the target design point. Full integration of a high-efficiency buck converter on the same die with a dualmicroprocessor is demonstrated to be feasible.Index Terms-Buck converter, dc-dc converter, dual supply voltage, high efficiency, integrated inductors, low power, low voltage, modeling of dc-dc converters, monolithic dc-dc conversion, multiple supply voltages, power supply, supply voltage scaling, switching dc-dc converters, voltage regulator.

Using adaptive processing to dynamically tune major microprocessor resources, developers can achieve greater energy efficiency with reasonable hardware and software overhead while avoiding undue performance loss.

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