A fast algorithm for finding common multiple-vertex dominators in circuit graphs

Krenz, René; Dubrova, Elena

doi:10.1145/1120725.1120954

Cited by 2 publications

(1 citation statement)

References 18 publications

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“…Successive improvements of the algorithms in [17] were done in [18][19][20] and [21]. The algorithm presented in [21] finds the set of all possible k-vertex dominators of a circuit by iteratively restricting the graph with respect to one of its vertices, v. The restriction is done by removing from the graph all vertices dominated by v. Dominators of size k − 1 are then computed for the resulting restricted graph by applying the same technique recursively.…”

Section: Previous Workmentioning

confidence: 99%

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs

Teslenko

Dubrova

Design, Automation and Test in Europe

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Dominators provide a general mechanism for identifying reconverging paths in graphs. This is useful for a number of applications in Computer-Aided Design (CAD) including signal probability computation in biased random simulation, switching activity estimation in power and noise analysis, and cut points identification in equivalence checking. However, traditional single-vertex dominators are too rare in circuit graphs. In order to handle reconverging paths more efficiently, we consider the case of double-vertex dominators which occur more frequently. First, we derive a number of specific properties of double-vertex dominators. Then, we describe a data structure for representing all double-vertex dominators of a given vertex in linear space. Finally, we present an algorithm for finding all double-vertex dominators of a given vertex in linear time. Our results provide an efficient systematic way of partitioning large graphs along the reconverging points of the signal flow.

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Section: Previous Workmentioning

confidence: 99%

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs

Teslenko

Dubrova

Design, Automation and Test in Europe

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Debugging RTL Using Structural Dominance

Mangassarian

Veneris

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-RTL debug has become a resource-intensive bottleneck in modern VLSI CAD flows, consuming as much as 32% of the total verification effort. This work aims to advance the state-of-the-art in automated RTL debuggers, which return all potential bugs in the RTL, called solutions, along with corresponding corrections. First, an iterative algorithm is presented to compute the dominance relationships between RTL blocks. These relationships are leveraged to discover implied solutions with every new solution, thus significantly reducing the number of formal engine calls. Furthermore, a modern SAT solver is tailored to detect debugging non-solutions, sets of RTL blocks guaranteed to be bug-free, and imply other non-solutions using the precomputed RTL dominance relationships. Extensive experiments on industrial designs show a three-fold reduction in the number of SAT calls due to solution implications, coupled with faster SAT run-times due to non-solution implications, resulting in a 2.63x overall speed-up in total SAT solving time, demonstrating the robustness and practicality of the proposed approach.

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A fast algorithm for finding common multiple-vertex dominators in circuit graphs

Cited by 2 publications

References 18 publications

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs

An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs

Debugging RTL Using Structural Dominance

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