A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation

Abstract

In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel percell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IRdrop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.

Test method and scheme for low-power validation in modern SOC integrated circuits

“…In [6], the authors show the use of a novel per-cell dynamic IR-drop estimation method. However, the target pattern selection process uses average power as a metric which is a drawback because peak power profile could be entirely different from average power.…”

“…From a DFT perspective, if the test patterns produce hypothetical activity levels, then the solution does not entail a PDN re-design but requires a power-efficient method of pattern generation. PSN follows a non-uniform distribution ondie and is localized to cell locations, where transitions occur [6]. When the magnitude of V droop exceeds the noise margin (V OH ), the gate would fail to switch, in turn, resulting in logic errors.…”

Identification of high power consuming areas with gate type and logic level information

“…Several methods are utilized in order to estimate power consumption or IR-drop [4][5][6][7][8][9][10][11][12][13]. Weighted switching activity (WSA) [4][5][6][7] is a very fast estimation technique, but it cannot directly estimate power consumption or IRdrop.…”

“…The methods [10,11] utilize WSA in a specific area, where the switching activity directly affects excessive delays on long sensitized paths. Method [12] [13] can accurately estimate the increase in IR-drop-induced delay, but method [13] can estimate them much faster than dynamic IR-drop analysis with commercial tools.…”

“…These methods [4][5][6][7][8][9][10][11][12][13] evaluate whether a given set test vectors cause excessive IR-drop or excessive delay. On the other hand, it is beneficial to utilize power-related information (such as locations where high power consumption or IR-drop occurs) before test vectors are generated [8].…”