A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy

Sheikh, Ahmad T.; Elrabaa, Muhammad E. S.; Sait, Sadiq M.

doi:10.1109/tvlsi.2016.2569532

Cited by 36 publications

(7 citation statements)

References 42 publications

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“…The selective redundancy technique [10] is applied to protect the transistors of a circuit that have relatively high POFi j. Sensitive transistors that have relatively high POF are identified based on fault simulation of random input patterns.…”

Section: Selective-transistor-redundancy-based Designmentioning

confidence: 99%

“…Algorithm 1 highlights the steps of the proposed method. Initially, the POF [10] of circuit under test is computed by first computing the POF of each transistor. The proposed algorithm applies transistor protection until the circuit POF reaches a predefined protection threshold, or a certain area overhead constraint is met.…”

Section: Selective-transistor-redundancy-based Designmentioning

confidence: 99%

See 1 more Smart Citation

A Review on Soft Errors and Different Fault Tolerance Techniques

Gadekar¹,

Patil²

2017

International Journal of Advanced Research in Computer and Comm

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With fabrication technology reaching nanolevels, systems are becoming more prone to manufacturing defects with higher susceptibility to soft errors. Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. A comprehensive review on the soft error generation and different fault tolerance techniques used, are presented in this study. After the overall concepts and general ideas are presented, representative works as well as new progress in the techniques are covered and discussed in detail.

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Section: Selective-transistor-redundancy-based Designmentioning

confidence: 99%

Section: Selective-transistor-redundancy-based Designmentioning

confidence: 99%

A Review on Soft Errors and Different Fault Tolerance Techniques

Gadekar¹,

Patil²

2017

International Journal of Advanced Research in Computer and Comm

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“…The drawback of effective protection mechanisms such as Quadded logic [8] is that they incur substantial performance, area and power overheads. Alternatively, there exist a set of selective hardening techniques that only protect the most sensitive elements of a combinational circuit, whether they are gates [9] or latches [10]. There is, therefore, a need for analysis tools that can provide the designer information about the most critical components of a circuit and the trade-off between the overheads of mechanisms for error resilience and the system-level SER value of the circuit.…”

Section: ç 1 Introductionmentioning

confidence: 99%

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

Anglada

Canal

Aragón

et al. 2021

IEEE Trans. Sustain. Comput.

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Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the design the susceptibility of combinational circuits to particle strikes. In the core of the framework lies MASkIt, a novel approach that combines signal probabilities with technology characterization to swiftly compute the logical, electrical, and timing masking effects of the circuit under study taking into account all input combinations and pulse widths at once. Signal probabilities are estimated applying a new hybrid approach that integrates heuristics along with selective simulation of reconvergent subnetworks. The experimental results validate our proposed technique, showing a speedup of two orders of magnitude in comparison with traditional fault injection estimation with an average estimation error of 5 percent. Finally, we analyze the vulnerability of the Decoder, Scheduler, ALU, and FPU of an out-of-order, superscalar processor design.

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“…The fabrication mechanism of improved to the nano levels and hence, the systems are needed to have higher susceptibility towards soft errors. Hence, Sheikh et al [14] had designed integrated circuits for minimum area overhead and soft error tolerance. The outcomes analysis suggest that the system has achieved significant reliability than another transistor sizing-based mechanism.…”

Section: Introductionmentioning

confidence: 99%

TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform

Kumar

Dinesha

2021

IJECE

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Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.

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A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy

Cited by 36 publications

References 42 publications

A Review on Soft Errors and Different Fault Tolerance Techniques

A Review on Soft Errors and Different Fault Tolerance Techniques

Fast and Accurate SER Estimation for Large Combinational Blocks in Early Stages of the Design

TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform

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