A fault tolerant journalized stack processor architecture

Ramazani, Abbas; Amin, Mohsin; Monteiro, Fabrice; Diou, Camille; Dandache, Abbas

doi:10.1109/iolts.2009.5196013

Cited by 3 publications

(2 citation statements)

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“…Our basic choice for the core processor was to select an architecture in the MISC family (Minimal Instruction Set Computer) instead of the more classic RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer) ones. Our architecture [28,29], inspired from that of the canonical stack processor [30], is able to offer a rather good level of performance with only a limited amount of hardware being required. Another interesting characteristic is the great compactness of the code running on this kind of processor.…”

Section: Overall Architectural Approachmentioning

confidence: 99%

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A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture

Amin¹,

Ramazani

Monteiro³

et al. 2011

International Journal of Reconfigurable Computing

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We introduce a specialized self-checking hardware journal being used as a centerpiece in our design strategy to build a processor tolerant to transient faults. Fault tolerance here relies on the use of error detection techniques in the processor core together with journalization and rollback execution to recover from erroneous situations. Effective rollback recovery is possible thanks to using a hardware journal and chosing a stack computing architecture for the processor core instead of the usual RISC or CISC. The main objective of the journalization and the hardware self-checking journal is to prevent data not yet validated to be sent to the main memory, and allow to fast rollback execution on faulty situations. The main memory, supposed to be fault secure in our model, only contains valid (uncorrupted) data obtained from fault-free computations. Error control coding techniques are used both in the processor core to detect errors and in the HW journal to protect the temporarily stored data from possible changes induced by transient faults. Implementation results on an FPGA of the Altera Stratix-II family show clearly the relevance of the approach, both in terms of performance/area tradeoff and fault tolerance effectiveness, even for high error rates.

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Section: Overall Architectural Approachmentioning

confidence: 99%

“…In case the sequence is not validated (see Figure 7), the SE data is restored from memory on rollback as the UVD in the SCHJ is dismissed, and execution is restarted from previous VP. Further explanation on the rollback operation can be found in [28].…”

Section: Journal Architecture and Operationmentioning

confidence: 99%