A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS

Wambacq, Piet; Giannini, Vito; Scheir, Karen; Thillo, Wim Van; Rolain, Yves

doi:10.1109/esscirc.2010.5619715

Cited by 42 publications

(27 citation statements)

References 5 publications

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“…The simulation results shows as the noise power spectral density reduction leads to Signal-To-Noise-Ratio (versus power) improvement comparing with the state-of-the-art [9,17]. Figure 29 shows the functional scheme of the filter.…”

Section: A 54 Db-dr 1-ghz-bandwidth Continuous-timementioning

confidence: 94%

Continuous Time Analog Filters Design in Nanometerscale CMOS Technologies

Matteis

Baschirotto

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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Analog filters are widely used in several kinds of integrated mixedsignal systems, since they are intrinsically needed for in-band signal selection, out-of-band noise rejection and anti-aliasing for the A-to-D (D-to-A) conversion. CMOS technological scaling down has already entered in nm-range scenario, leading to severe degradation of some of the most important MOS device performance for analog design. Among them, lower V DD /V TH ratio (supply voltage and threshold voltage, respectively), higher power consumption, and transistor intrinsic gain decreasing. On the other side the increasing MOS transistor transconductance (g m ) and transition frequency (f T ) enables tens of GHz applications, which take advantage of cheaper and smart CMOS processes. Specific continuoustime analog filters will be presented in this chapter, with the aim to introduce novel circuital topologies or optimizations and techniques suitable to mitigate the severe issues present in sub-90 nm CMOS technological nodes, and at the same time to exploit the opportunity of higher technological scaling-down.

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Section: A 54 Db-dr 1-ghz-bandwidth Continuous-timementioning

confidence: 94%

Continuous Time Analog Filters Design in Nanometerscale CMOS Technologies

Matteis

Baschirotto

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…Recently, the Super-Source-Follower (SSF) architecture has been used for an efficient fully differential Sallen-Key implementation [7], exhibiting very large bandwidth and low in-band noise, at the cost of an additional power budget for Sallen-Key out-of-band zeros rejection.…”

Section: Imentioning

confidence: 99%

A 33-MHz 70dB-SNR super-source-follower-based low-pass analog filter

Matteis

Pezzotta

D'Amico

et al. 2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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In this paper a 4 th -order low-pass continuous-time analog filter is presented. A smart and compact biquadratic cell has been realized using the super-source-follower circuit. The biquadratic cell synthesizes a 2 nd -order low-pass transfer function, using only two capacitors and four transistors per stage: two transistors for g m -C transfer function and two transistors as current sources for biasing purpose.A 4 th -order filter prototype has been integrated in CMOS 0.18μm technological node. The achieved Signal-to-Noise-Ratio is 70dB, with 8nV/√Hz in-band input referred noise. In-Band IIP3 is 18dBm. The current consumption for the entire 4 th -order filter is 770μA, from a single 1.8V supply voltage.

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“…The main drawback of passive on-chip implementations of this LPF is the large area of the inductors or capacitors required and their low quality factor [7] [8]. Recently, a few wideband active filters that can occupy a lesser area also have been proposed for receivers [9] [10]. However, they are challenging to design and can limit the transmitter linearity as compared to passive filters.…”

Section: Characteristics Of Nyquist Dacsmentioning

confidence: 99%

“…The passive filters occupy a large on-chip area and have a low quality factor [7]. While some low-area high-order wideband active filters have also been recently reported [9,10], they are challenging to design and impact the transmitter linearity.…”

Section: Introductionmentioning

confidence: 99%

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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A fifth-order 880MHz/1.76GHz active lowpass filter for 60GHz communications in 40nm digital CMOS

Cited by 42 publications

References 5 publications

Continuous Time Analog Filters Design in Nanometerscale CMOS Technologies

Continuous Time Analog Filters Design in Nanometerscale CMOS Technologies

A 33-MHz 70dB-SNR super-source-follower-based low-pass analog filter

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

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