A Fin-type independent-double-gate NFET

Fried, D.; Nowak, E.; Kedzierski, J.; Duster, J.S.; Komegay, K.T.

doi:10.1109/drc.2003.1226864

Cited by 23 publications

(15 citation statements)

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“…Typically the front and back gates of DG devices are connected together resulting in a 3-Terminal (3-T) device. 3-T devices can be used Recently, double gate devices with independent gate control option (separate contacts for back and front gates) have been developed [9][10]. Such DG devices are referred to as Independent or Isolated Gate (IG) devices (Fig.…”

Section: Double Gate Soi Devicesmentioning

confidence: 99%

“…bulk-CMOS) can be directly translated to DG technology by replacing each transistor with a connected gate (3-T) DGMOS, where the front and the back gates are tied together. However, the directly translated circuit style does not utilize possibility of independent control of front and back gates (4-T configuration) [9][10]. The fabrication of both 3-T and 4-T DG on the same process has been recently reported [10].…”

Section: Logic Design Using Double Gate Devicesmentioning

confidence: 99%

“…1(d)) [8]. Double gate devices with isolated gates (independent gates) are also being developed [9][10]. Independent gate option can be useful for low power and mixed signal applications [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

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Double-gate SOI devices for low-power and high-performance applications

Roy

Mahmoodi

Mukhopadhyay

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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Abstract:Double-Gate (DG) IntroductionThe scaling of conventional bulk CMOS technology is facing great challenges due to increased leakage and process variations with scaling down of device dimensions. Channel engineering techniques such as retrograde well and halo implantation are introduced to improve scalability and performance of such devices ( Fig. 1(a)) [1,2]. However, the scalability of such a device structure is limited due to increased short channel effects [3]. This has motivated the need for nonclassical silicon devices to extend CMOS scaling beyond 45nm node ( Fig. 1(b-d)). Ultra thin body SOI FETs employ very thin silicon body to achieve better control of the channel by the gate, and hence, reduced leakage and short channel effects. Use of intrinsic or lightly doped body reduces threshold voltage (Vt) variations due to random dopant fluctuations [4] and enhances the mobility of careers in the channel region and therefore ON current. In these devices, there can be a weak common back gate that is shared as a common substrate among all the transistors. Such a process is referred to as Ground Plane SOI (GP-SOI) [31]. Better scalability can be achieved by introduction of a second gate at the other side of the body of each transistor resulting in a Double Gate (DG) SOI structure ( Fig. 1(c)). Due to excellent control of short channel effects, double-gate SOI devices have emerged as the device of choice for circuit design in sub-50nm regime [5]. Low subthreshold leakage and higher ON current in DG devices make them suitable for circuit design in sub-50nm regime [6][7]. There are a variety of device structures suitable for double gate technologies. One of the promising structures is FinFET ( Fig. 1(d)) [8]. Double gate devices with isolated gates (independent gates) are also being developed [9][10]. Independent gate option can be useful for low power and mixed signal applications [10][11][12][13][14]. Such developments at the device level provide opportunities for new ways of circuit design for low power and high performance. In this paper, we first review the device design options for the double gate device structures (Section 2). Then, we discuss the circuit design options using such devices for logic and memory applications (Section 3 and 4). Double Gate SOI DevicesA classification of DG devices and their implications on circuit design is illustrated in Fig. 2. There are two main device processes possible for DG devices ( Fig. 2 and 3), namely (a) symmetric device with same gate material (e.g. near-midgap metals) and oxide thickness for the front and the back gate [15][16] and (b) asymmetric device with different strengths for front and back gates. Different strengths can be obtained by using either different oxide thickness (asymmetric oxide) [17] or materials of different work-function (e.g. n+ poly and p+ poly) for the front and the back gate (asymmetric work-function) [15].Regardless of the underlying device process, DG devices can also be classified in terms of their structure (Fig. 2). Typicall...

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Section: Double Gate Soi Devicesmentioning

confidence: 99%

Section: Logic Design Using Double Gate Devicesmentioning

confidence: 99%

See 1 more Smart Citation

Double-gate SOI devices for low-power and high-performance applications

Roy

Mahmoodi

Mukhopadhyay

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

View full text Add to dashboard Cite

show abstract

“…This is because: Fig. 3 [6][7]. This analysis represents the current difference between two identical transistors, both with front gate at V DD but with different back gate bias.…”

Section: Device Characteristicsmentioning

confidence: 99%

“…bulk-CMOS) can be directly translated into the DG technology by replacing each transistor with a connected gate DGMOS (ConnGateDG), where the front and the back gates are tied together. However, the Directly Translated circuit (DirTrans) style does not utilize possibility of independent control (IndGateDG) of front and back gates [6][7]. The fabrication of both ConnGateDG and IndGateDG on the same process has been recently reported [7].…”

Section: Introductionmentioning

confidence: 99%