Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET

Mukhopadhyay, Saibal; Mahmoodi, Hamid; Roy, Kaushik

doi:10.1109/isqed.2005.44

Cited by 18 publications

(12 citation statements)

References 14 publications

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“…Existing Circuits Fig.2 presents the Latch Based Sense Amplifier (LBSA) derived from [3]. OUTL and OUTR are being precharged to 0V before sensing.…”

Section: Sense Amplifiers For Srammentioning

confidence: 99%

An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

Nasalski

Makosiej

Giraud

et al. 2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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“…Existing Circuits Fig.2 presents the Latch Based Sense Amplifier (LBSA) derived from [3]. OUTL and OUTR are being precharged to 0V before sensing.…”

Section: Sense Amplifiers For Srammentioning

confidence: 99%

An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

Nasalski

Makosiej

Giraud

et al. 2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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“…The main design concerns in sense amplifiers include sensing delay, power, and tolerance to mismatch and process variations. It is shown that independent gate operation can be used to improve the design of a sense amplifier [11]. Fig.…”

Section: 2) Sense Amplifier Design In Dg Soimentioning

confidence: 99%

“…Such a short circuit prevention circuit is proposed in [11]. The short-circuit power can also be reduced by using asymmetric devices for N1 and N2, and connecting the back gates to BLB and BL.…”

Section: 2) Sense Amplifier Design In Dg Soimentioning

confidence: 99%

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Double-gate SOI devices for low-power and high-performance applications

Roy

Mahmoodi

Mukhopadhyay

et al. 2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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Abstract:Double-Gate (DG) IntroductionThe scaling of conventional bulk CMOS technology is facing great challenges due to increased leakage and process variations with scaling down of device dimensions. Channel engineering techniques such as retrograde well and halo implantation are introduced to improve scalability and performance of such devices ( Fig. 1(a)) [1,2]. However, the scalability of such a device structure is limited due to increased short channel effects [3]. This has motivated the need for nonclassical silicon devices to extend CMOS scaling beyond 45nm node ( Fig. 1(b-d)). Ultra thin body SOI FETs employ very thin silicon body to achieve better control of the channel by the gate, and hence, reduced leakage and short channel effects. Use of intrinsic or lightly doped body reduces threshold voltage (Vt) variations due to random dopant fluctuations [4] and enhances the mobility of careers in the channel region and therefore ON current. In these devices, there can be a weak common back gate that is shared as a common substrate among all the transistors. Such a process is referred to as Ground Plane SOI (GP-SOI) [31]. Better scalability can be achieved by introduction of a second gate at the other side of the body of each transistor resulting in a Double Gate (DG) SOI structure ( Fig. 1(c)). Due to excellent control of short channel effects, double-gate SOI devices have emerged as the device of choice for circuit design in sub-50nm regime [5]. Low subthreshold leakage and higher ON current in DG devices make them suitable for circuit design in sub-50nm regime [6][7]. There are a variety of device structures suitable for double gate technologies. One of the promising structures is FinFET ( Fig. 1(d)) [8]. Double gate devices with isolated gates (independent gates) are also being developed [9][10]. Independent gate option can be useful for low power and mixed signal applications [10][11][12][13][14]. Such developments at the device level provide opportunities for new ways of circuit design for low power and high performance. In this paper, we first review the device design options for the double gate device structures (Section 2). Then, we discuss the circuit design options using such devices for logic and memory applications (Section 3 and 4). Double Gate SOI DevicesA classification of DG devices and their implications on circuit design is illustrated in Fig. 2. There are two main device processes possible for DG devices ( Fig. 2 and 3), namely (a) symmetric device with same gate material (e.g. near-midgap metals) and oxide thickness for the front and the back gate [15][16] and (b) asymmetric device with different strengths for front and back gates. Different strengths can be obtained by using either different oxide thickness (asymmetric oxide) [17] or materials of different work-function (e.g. n+ poly and p+ poly) for the front and the back gate (asymmetric work-function) [15].Regardless of the underlying device process, DG devices can also be classified in terms of their structure (Fig. 2). Typicall...

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“…However, double gate SOI MOSFETs offer the same flexibility as PD SOI single gate MOSFETs with regard to this dynamic Vth adjustment. Moreover, it has been demonstrated that an independent control of front and back gates can be exploited to reduce both dynamic power and sensing delay in a sense amplifier design [6]. It can also be used to merge parallel transistors [7] and thus reduce dynamic power through the reduction of parasitic capacitance, as well as static power.…”

Section: Introductionmentioning

confidence: 99%

Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs

O’Connor

Hassoune

Navarro

2010

IFIP Advances in Information and Communication Technology

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Abstract. This work presents a new style of gate-level reconfigurable cells based on the double-gate (DG) MOSFET device. The proposed dynamic-and static-logic cells demonstrate significant gate area reductions compared to conventional CMOS lookup table (LUT) techniques (between 80-95%) while configuration memory requirements are also reduced (up to 60%). Simulation results show that it can be used either in low power reconfigurable applications (up to 90% power reduction is possible) or for speeds comparable to those of CMOS-LUTs.

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Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET

Abstract: Double-Gate (DG)

Cited by 18 publications

References 14 publications

An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

Double-gate SOI devices for low-power and high-performance applications

Fine-Grain Reconfigurable Logic Cells Based on Double-Gate MOSFETs

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