Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction

Agostinelli, Matteo; Alioto, Massimo; Esseni, D.; Selmi, L.

doi:10.1007/978-3-540-95948-9_4

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…A large number of research articles have been published that demonstrate the improved short-channel behavior of these devices over conventional bulk MOSFETs [19][20][21][22][31][32][33]. Many researchers have presented novel circuit design styles that exploit different kinds of FinFETs [34][35][36][37][38][39][40][41][42][43][44][45][46][47][48]. Researchers have also explored various symmetric and asymmetric FinFET styles and used them in hybrid FinFET logic gates and memories [49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66].…”

Section: Introductionmentioning

confidence: 99%

FinFETs: From Devices to Architectures

Bhattacharya

Jha

2014

Advances in Electronics

164

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Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

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Section: Introductionmentioning

confidence: 99%

FinFETs: From Devices to Architectures

Bhattacharya

Jha

2014

Advances in Electronics

164

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“…9(b)] occupies 27% more area than size X2 SG-NAND2, with a staggered pull-up network of parallel FinFETs, and shared back-gate contacts for the series pull-down FinFETs. Mixed terminal (MT-) NAND2[16] is identical to LP-NAND2 in area, with NB in SG mode [Fig. 7(c)].…”

mentioning

confidence: 99%

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology

Bhoj

Jha

2011

2011 12th International Symposium on Quality Electronic Design

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Multi-gate CMOS devices promise to usher an era of transistors with good electrostatic integrity at the sub-22nm nodes, which makes it essential to rethink traditional approaches to designing lowleakage digital logic and sequential elements formerly used in highperformance planar single-gate technologies. In the current work, we explore the design space of symmetric (Symm-Φ G ) and asymmetric gate workfunction (Asymm-Φ G ) FinFET logic gates, latches, and flip-flops for optimal trade-offs in leakage vs. delay and temperature in a highperformance FinFET technology. We demonstrate, using mixed-mode Sentaurus technology computer-aided design (TCAD) device simulations, that Asymm-Φ G shorted-gate n/p-FinFETs, which use both workfunctions corresponding to typical high-performance n/p-FinFETs, yield over two orders of magnitude lower leakage without excessive degradation in onstate current, in comparison to Symm-Φ G shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independentgate (IG) FinFETs for leakage reduction. Results for elementary logic gates like INV, NAND2, NOR2, XOR2, and XNOR2 using Asymm-Φ G SG-mode FinFETs indicate that they are more optimally located in the leakage-delay spectrum in comparison to the most versatile configurations possible by mixing corresponding Symm-Φ G SG-and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-Φ G and Asymm-Φ G FinFETs to optimize leakage, delay, and setup time simultaneously.

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