A fine-grain, high-throughput architecture using through-wafer optical interconnect

Lacy, W.S.; Camperi-Ginestet, C.; Buchanan, B.; Wills, D.S.; Jokerst, N.M.; Brooke, M.A.

doi:10.1109/mppoi.1994.336641

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Cited by 8 publications

(1 citation statement)

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“…Each node occupies a square area of 1 cm 2 and is separated by 0.5 cm from its neighbors for a minimum connection path of 1.5 cm (die only). Recent studies confirm that packaging of multiprocessor free-space optical interconnects at this level of compaction is feasible [28,29]. The VCSEL and P-I-N detector arrays are integrated on top of the CMOS circuits via flip chip bonding [30].…”

Section: Latency Comparisonmentioning

confidence: 99%

Modeling Free-Space Opticalk-aryn-Cube Wormhole Networks

Raksapatcharawong¹,

Pinkston²

1998

Journal of Parallel and Distributed Computing

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Section: Latency Comparisonmentioning

confidence: 99%

Modeling Free-Space Opticalk-aryn-Cube Wormhole Networks

Raksapatcharawong¹,

Pinkston²

1998

Journal of Parallel and Distributed Computing

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Design issues for core-based optoelectronic chips: a case study of the WARRP network router

Raksapatcharawong

Pinkston

1999

IEEE J. Select. Topics Quantum Electron.

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Communication through stacked silicon circuitry using integrated thin film InP-based emitters and detectors

Jokerst

Camperi-Ginestet

Buchanan

et al. 1995

IEEE Photon. Technol. Lett.

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To demonstrate optical communication through stacked silicon circuitry, thin film InGaAsP-based emitters and photodetectors have been bonded directly onto silicon circuitry. These optoelectronic devices operate at a wavelength to which silicon is transparent. The thin film emitters and detectors were integrated onto a MOSIS foundry silicon CMOS integrated circuit which contained driver and amplifier circuits. Bidirectional vertical optical communication between two layers of circuitry was demonstrated by stacking the layers, exciting the emitter driver circuit on one layer with an electrical signal, and measuring the output electrical signal from the detector amplifier located on the other circuit in the vertical stack.

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A fine-grain, high-throughput architecture using through-wafer optical interconnect

Cited by 8 publications

References 15 publications

Modeling Free-Space Opticalk-aryn-Cube Wormhole Networks

Modeling Free-Space Opticalk-aryn-Cube Wormhole Networks

Design issues for core-based optoelectronic chips: a case study of the WARRP network router

Communication through stacked silicon circuitry using integrated thin film InP-based emitters and detectors

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