A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

Jee, Dong-Woo; Suh, Yunjae; Kim, Byungsub; Park, Hong-June; Sim, Jae‐Yoon

doi:10.1109/jssc.2013.2282620

Cited by 31 publications

(9 citation statements)

References 15 publications

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“…They are used in a variety of applications, e.g., clock-and data recovery (CDR) circuits [1], [2], for phase acquisition in phase-locked loops (PLL) [3], [4], phase ramp generator in sub-sampling PLLs [5]. A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Jakobsson

Serban²,

Gong³

2019

IEEE Trans. Circuits Syst. II

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Abstract-This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm 2 .

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Section: Introductionmentioning

confidence: 99%

“…A PI can potentially replace a digital-to-time converter (DTC) in many applications to generate a time delay. Several PI topologies have been proposed; Delay line based [6], [7], trigonometric [2], [8], [9], current-weighting [1], [3], [4], [10], [11], charge-steering [12] and constant-slope charging [5], [13].…”

Section: Introductionmentioning

confidence: 99%

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Jakobsson

Serban²,

Gong³

2019

IEEE Trans. Circuits Syst. II

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show abstract

“…This methodology delivers good noise suppression but it introduces much delay to the system. The use of finite impulse response (FIR) filters [18] and infinite impulse response (IIR) filters [19] is well studied too for this application. The problem when using FIR filters is that it is common that a high order of the filter is required to obtain satisfactory results.…”

Section: Introductionmentioning

confidence: 99%

Vibration Suppression for Improving the Estimation of Kinematic Parameters on Industrial Robots

Elvira-Ortiz

Romero-Troncoso

Jaen-Cuéllar

et al. 2016

Shock and Vibration

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Vibration is a phenomenon that is present on every industrial system such as CNC machines and industrial robots. Moreover, sensors used to estimate angular position of a joint in an industrial robot are severely affected by vibrations and lead to wrong estimations. This paper proposes a methodology for improving the estimation of kinematic parameters on industrial robots through a proper suppression of the vibration components present on signals acquired from two primary sensors: accelerometer and gyroscope. A Kalman filter is responsible for the filtering of spurious vibration. Additionally, a sensor fusion technique is used to merge information from both sensors and improve the results obtained using each sensor separately. The methodology is implemented in a proprietary hardware signal processor and tested in an ABB IRB 140 industrial robot, first by analyzing the motion profile of only one joint and then by estimating the path tracking of two welding tasks: one rectangular and another one circular. Results from this work prove that the sensor fusion technique accompanied by proper suppression of vibrations delivers better estimation than other proposed techniques.

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“…1 shows circuit diagram of the proposed PLL which follows an overall architecture of phase rotator (PR) based fractional division scheme. The phase rotator is implemented with a dual-referenced interpolator [8] controlled by a 3rd order DSM output. An LC-DCO generates complementary 1.9GHz outputs followed by two toggle D-flipflops providing four-phase 950 MHz.…”

Section: Introductionmentioning

confidence: 99%

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

Lee¹,

Jee²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a 1.9-GHz digital ΔΣ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in 0.11-μm CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

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A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL

Cited by 31 publications

References 15 publications

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

A Low-Noise <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula>-Based Phase Interpolator in 16-nm CMOS

Vibration Suppression for Improving the Estimation of Kinematic Parameters on Industrial Robots

An In-Band Noise Filtering 32-tap FIR-Embedded ΔΣ Digital Fractional-N PLL

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