A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components Codes

Piriou, Erwan; Jego, C.; Adde, Patrick; Jézéquel, Michel

doi:10.1109/isvlsi.2006.2

Cited by 4 publications

(2 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As will be demonstrated by the examples, the basic algorithm described above performs very well as a SISO decoder for the constituent codes in a composite turbo-like code such as a turbo product code [3]. It also performs well as a soft-in decoder for relatively small distance block codes such as extended Hamming codes and low-distance BCH codes.…”

Section: Siso Algorithm I)mentioning

confidence: 90%

“…Throughput, power, and gate count considerations dictate that, for efficient realization of decoders, both algorithm and architecture need to be optimized to meet design and performance requirements. Recently a number of softdecision decoding algorithms [1][2][3][4][5][6][7] have been proposed for decoding linear block codes. The optimal soft-in soft-out (SISO) decoder is based upon maximum a posteriori probability (APP).…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An FPGA implementation of a soft-in soft-out decoder for block codes

Abdul-Shakoor

Kerr

Lodge

et al. 2008

2008 24th Biennial Symposium on Communications

View full text Add to dashboard Cite

This paper presents an FPGA implementation of the Vector SISO algorithm for the (64, 57) extended Hamming code (EH) and (64, 51) extended Bose, Chaudhri, and Hocquenghem code (EBCH). The decoder architecture is defined in VHDL and the circuit is implemented on a Xilinx XC2VP100-1704ff-5 FPGA device. To achieve the required throughput, a pipelined data path architecture operating off a master clock was selected. To reduce gate count, the dynamic range of intermediate results was limited through use of saturation arithmetic. The decoder functionality was verified by means of a test bench that compared the decoded bit stream with error free transmitted signals. SISO decoder design choices that impact the bit error rate (BER) are also presented.

show abstract

Section: Siso Algorithm I)mentioning

confidence: 90%