2008 24th Biennial Symposium on Communications 2008
DOI: 10.1109/bsc.2008.4563244
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An FPGA implementation of a soft-in soft-out decoder for block codes

Abstract: This paper presents an FPGA implementation of the Vector SISO algorithm for the (64, 57) extended Hamming code (EH) and (64, 51) extended Bose, Chaudhri, and Hocquenghem code (EBCH). The decoder architecture is defined in VHDL and the circuit is implemented on a Xilinx XC2VP100-1704ff-5 FPGA device. To achieve the required throughput, a pipelined data path architecture operating off a master clock was selected. To reduce gate count, the dynamic range of intermediate results was limited through use of saturatio… Show more

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Cited by 2 publications
(1 citation statement)
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“…The algorithm is a soft-in soft-out decoding algorithm. Versions of the algorithm for binary codes have been described in [17][18][19]. For this application, the algorithm was modified to return hard decisions only.…”
Section: Decoding Algorithmmentioning
confidence: 99%
“…The algorithm is a soft-in soft-out decoding algorithm. Versions of the algorithm for binary codes have been described in [17][18][19]. For this application, the algorithm was modified to return hard decisions only.…”
Section: Decoding Algorithmmentioning
confidence: 99%