A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Shen, Kun-Yi; Farooq, Syed Feruz Syed; Fan, Y.; Nguyen, Kimchau N.; Wang, Qi; Neidengard, Mark; Kurd, Nasser; Elshazly, Amr

doi:10.1109/tcsi.2017.2784319

Cited by 10 publications

(1 citation statement)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To solve this problem, Ref. [32] reported a sourceswitched CP with reverse leakage compensation technique, as shown in Fig. 6(d), which combines the advantages of the CPs shown in Figs.…”

Section: Reference Spur Suppression Techniquementioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

View full text Add to dashboard Cite

CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

show abstract

“…To solve this problem, Ref. [32] reported a sourceswitched CP with reverse leakage compensation technique, as shown in Fig. 6(d), which combines the advantages of the CPs shown in Figs.…”

Section: Reference Spur Suppression Techniquementioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

View full text Add to dashboard Cite

show abstract

Planar Growth, Integration, and Applications of Semiconducting Nanowires

Sun

Dong

et al. 2019

Advanced Materials

View full text Add to dashboard Cite

Silicon and other inorganic semiconductor nanowires (NWs) have been extensively investigated in the last two decades for constructing high‐performance nanoelectronics, sensors, and optoelectronics. For many of these applications, these tiny building blocks have to be integrated into the existing planar electronic platform, where precise location, orientation, and layout controls are indispensable. In the advent of More‐than‐Moore's era, there are also emerging demands for a programmable growth engineering of the geometry, composition, and line‐shape of NWs on planar or out‐of‐plane 3D sidewall surfaces. Here, the critical technologies established for synthesis, transferring, and assembly of NWs upon planar surface are examined; then, the recent progress of in‐plane growth of horizontal NWs directly upon crystalline or patterned substrates, constrained by using nanochannels, an epitaxial interface, or amorphous thin film precursors is discussed. Finally, the unique capabilities of planar growth of NWs in achieving precise guided growth control, programmable geometry, composition, and line‐shape engineering are reviewed, followed by their latest device applications in building high‐performance field‐effect transistors, photodetectors, stretchable electronics, and 3D stacked‐channel integration.

show abstract

A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop

Han,

Tong

2024

AEU - International Journal of Electronics and Communications

View full text Add to dashboard Cite

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Cited by 10 publications

References 8 publications

CMOS analog and mixed-signal phase-locked loops: An overview

CMOS analog and mixed-signal phase-locked loops: An overview

Planar Growth, Integration, and Applications of Semiconducting Nanowires

A current-configurable charge pump with current mismatch compensation for wide output frequency range phase-locked loop

Contact Info

Product

Resources

About