A floating-point CORDIC based SVD processor

Liu, Z.; Dickson, K.; McCanny, J.V.

doi:10.1109/asap.2003.1212843

Cited by 11 publications

(3 citation statements)

References 13 publications

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“…Futher work will include applicability of our architecture to other MIMO argorithms. In fact, it is well known that the CORDIC operator could be used to implement different communication functions in the Software Defined Radio (SDR) system [11], and as well to compute the SVD decomposition as shown in [12]. So our architecture can be also used to realize these applications simply by changing the sequences of dynamic reconfigurations between CORDIC operators.…”

Section: Discussionmentioning

confidence: 94%

An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management

Wang

Leray

Palicot

2008

2008 IEEE International Conference on Communications

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This paper introduces a reconfigurable MIMO V-BLAST (Vertical Bell Laboratories Layered Space-Time) square root decoder that is CORDIC operators based, allows for dynamically changing the interconnections between the CORDIC (COordinate Rotation DIgital Computer) operators.These interconnections of CORDIC operators are implemented in a partial reconfigurable part of FPGA using the dynamic reconfiguration method which improves both the reconfiguration time and the area efficiency. Moreover, this reconfiguration time improvement is increased thanks to the MicroBlaze (within the FPGA) in which is included the reconfiguration management. This MIMO square root decoder is mapped on a Xilinx Virtex-4, showing the configuration time improvement, area efficiency and flexibility of the decoder by using the dynamic partial reconfiguration method.

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Section: Discussionmentioning

confidence: 94%

An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management

Wang

Leray

Palicot

2008

2008 IEEE International Conference on Communications

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“…According to the authors, this hybrid processor possesses sufficient accuracy to compute QRD and other matrix computation. A similar approach was used in [16] to implement an SVD processor. Again, an iterative CORDIC architecture is also used, but a two-stage pipeline of the datapath allows performing two independent rotations at the same time.…”

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

Efficient Floating-Point Givens Rotation Unit

Hormigo,

Muñoz

2020

Preprint

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High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. FPGA implementation results are also presented and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput.

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“…According to the authors, this hybrid processor possesses sufficient accuracy to compute QRD and other matrix computations. A similar approach was used in [17] to implement an SVD processor. Again, an iterative CORDIC architecture is also used, but a two-stage pipeline of the datapath allows performing two independent rotations at the same time.…”

Section: Previous Work On Fp Cordic and Fp Givens Rotationmentioning

confidence: 99%

Efficient Floating-Point Givens Rotation Unit

Hormigo

Muñoz

2020

Circuits Syst Signal Process

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High-throughput QR decomposition is a key operation in many advanced signal processing and communication applications. For some of these applications, using floating-point computation is becoming almost compulsory. However, there are scarce works in hardware implementations of floating-point QR decomposition for embedded systems. In this paper, we propose a very efficient high-throughput floating-point Givens rotation unit for QR decomposition. Moreover, the initial proposed design for conventional number formats is enhanced by using the new Half-Unit Biased format. The provided error analysis shows the effectiveness of our proposals and the trade-off of different implementation parameters. We also present FPGA implementation results and a thorough comparison between both approaches. These implementation results also reveal outstanding improvements compared to other previous similar designs in terms of area, latency, and throughput.

show abstract

A floating-point CORDIC based SVD processor

Cited by 11 publications

References 13 publications

An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management

An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management

Efficient Floating-Point Givens Rotation Unit

Efficient Floating-Point Givens Rotation Unit

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