An Efficient MIMO V-BLAST Decoder Based on a Dynamically Reconfigurable FPGA Including its Reconfiguration Management

Abstract

This paper introduces a reconfigurable MIMO V-BLAST (Vertical Bell Laboratories Layered Space-Time) square root decoder that is CORDIC operators based, allows for dynamically changing the interconnections between the CORDIC (COordinate Rotation DIgital Computer) operators.These interconnections of CORDIC operators are implemented in a partial reconfigurable part of FPGA using the dynamic reconfiguration method which improves both the reconfiguration time and the area efficiency. Moreover, this reconfiguration time improvement is increased thanks to the MicroBlaze (within the FPGA) in which is included the reconfiguration management. This MIMO square root decoder is mapped on a Xilinx Virtex-4, showing the configuration time improvement, area efficiency and flexibility of the decoder by using the dynamic partial reconfiguration method.

Implementations of FFT and STBD for MIMO-OFDM on a Reconfigurable Baseband Platform

“…Most of the existing reconfigurable architectures use an FPGA computational model which consists of a set of finegrained to medium-grained homogenous modules [6], [7], or embedded reconfigurable logic cores [8]. While such techniques provide good flexibility and work well with compilation tools, they can lead to a high interconnection comCopyright c 2010 The Institute of Electronics, Information and Communication Engineers plexity.…”

“…[10] uses a GPP/DSP core with accelerators, and [8] uses an FPGA core. [9], [20], [21] are homogenous coarse-grained reconfigurable architectures with specifically designed modules.…”