A Flow Graph Semantics of VHDL: A Basis for Hardware Verification with VHDL

Reetz, Ralf; Kropf, Thomas

doi:10.1007/978-1-4615-2237-9_8

Cited by 5 publications

(3 citation statements)

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“…In our previous work [27,28,29,30], we have set up a formal semantics of VHDL in higher order logic. Everything was realized in HOL90: the formalization of VHDL by deep embedding as well as first formal proofs.…”

Section: A Formal Environment For Vhdlmentioning

confidence: 99%

Evaluating Possibilities for Formally Sound Simulation and Verification of VHDL

Reetz¹,

Kropf²

1996

Electronic Workshops in Computing

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Formal verification is a promising way to ensure correctness of digital cuircuits. VHDL is an important standard in descripting digital circuits. This paper gives a survey about the state of the art in bringing formal verification and VHDL together. Up to now, there is no unique and best solution for the formal verification of arbitrary descriptions. The survey notes serveral aspects, which has been traded off against each other: "degree of automation", "supported VHDL subset", "practical usability", "confidence of the approach", to name just some. The existing approaches are compared with redard to these aspects. The reader gets an overview of the possibilities and limitations of different approaches with regard to simulation, symbolic simulation and formal verification. Finally, the formal VHDL environment created by the authors is presented.

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Section: A Formal Environment For Vhdlmentioning

confidence: 99%

Evaluating Possibilities for Formally Sound Simulation and Verification of VHDL

Reetz¹,

Kropf²

1996

Electronic Workshops in Computing

Self Cite

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“…Most of these works (except a few trials [5,20,21]) were considered just as theoretical frameworks because they treat only subsets of VHDL and they are not faithful to the LRM (Language Reference Manual). The Boerger 's work [5] is one of the successful and faithful analysis for almost full VHDL by ASM (Abstract State Machine), and its extended works give practical contributions [7,8,9] to the language validation in VHDL-AMS.…”

Section: Introductionmentioning

confidence: 99%

A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Sasaki

1999

Proceedings of the Conference on Design, Automation and Test in Europe

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A formal semantic analysis for Verilog-HDL and VHDL is provided in order to give the simulation model especially focusing on signal scheduling and timing control mechanism. Our semantics is faithful to LRM and is expected to become a coherent first step for a future semantic interoperability analysis on multisemantic-domain such as Verilog-AMS and VHDL-AMS. By ignoring the differences of the two simulation cycles, we can use the common semantic functions and the common simulation cycle.

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“…If a formal semantics on the lowest time abstraction level [17], the simulation cycle, is used, then all positions are allowed. If a formal semantics is used, which executes all sequential statements between two wait statements within one step (as it is usually done for e.g.…”

Section: Formal Specifications In Vhdlmentioning

confidence: 99%

Formal specification in VHDL for hardware verification

Reetz¹,

Schneider²,

Kropf³

Proceedings Design, Automation and Test in Europe

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In this paper, we enrich VHDL with new specification constructs intended for hardware verification. Using our extensions, total correctness properties may now be stated whereas only partial correctness can be expressed using the standard VHDL assert statement. All relevant properties can now be specified in such a way that the designer does not need to use formalisms like temporal logics. As the specifications are independent from a certain formalism, there is no restriction to a certain hardware verification approach.

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A Flow Graph Semantics of VHDL: A Basis for Hardware Verification with VHDL

Cited by 5 publications

References 0 publications

Evaluating Possibilities for Formally Sound Simulation and Verification of VHDL

Evaluating Possibilities for Formally Sound Simulation and Verification of VHDL

A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine

Formal specification in VHDL for hardware verification

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