A flowgraph semantics of VHDL: Toward a VHDL verification workbench in HOL

Abstract

VHDL-based verification methods require a formalized semantics of this hardware description language. As it has been shown recently that flowgraphs are an excellent means for defining the semantics of VHDL, we also use them to formalize full VHDL. However, our approach differs in important aspects from previous works. We use flowgraphs as an intermediate level for facilitating the deep embedding of VHDL in higher order logics, i.e. each VHDL program directly is a well-formed formula of the logic itself. This leads to a transparent semantic definition, since all constructs are defined explicitly as conservative extensions of the logic, and allows the direct reasoning about VHDL constructs. The relevant constructs of VHDL have been formalized, including delta delay. As we provide a general verification framework, different verification techniques such as model-checking, first--order theorem proving or invariant-based approaches may be used, depending on the verification task.

Formale Methoden bei der Spezifikation von Hardware

“…Daher basieren die VHDL-spezifischen Ansätze auf anderen Formalismen, wie z.B. auf Petrinetzen, dynamischen Algebren oder auf dezidierten Formalisierungen mit verschiedenen Logiken wie Logik hö-herer Ordnung [8]. Dabei eignen sich naturgemäß logikbasierte Semantiken besser für die Verifikation, da in diesem Fall direkt ein formales System zum logischen Schlußfolgern zur Verfügung steht, im allgemeinen direkt unterstützt durch ein rechnergestütztes Beweissystem.…”

Evaluating Possibilities for Formally Sound Simulation and Verification of VHDL

“…In our approach proposed in [29], the test bench concept usually used in VHDL simulations is adapted for property specifications, which we call a "verification bench". A verification bench contains two parts: the implementation on the one hand and watchdogs on the other hand.…”

“…In our previous work [27,28,29,30], we have set up a formal semantics of VHDL in higher order logic. Everything was realized in HOL90: the formalization of VHDL by deep embedding as well as first formal proofs.…”