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This paper reports on a new bottom-up synthesis technique for general behavioral descriptions. Our technique extends traditional straight-line code synthesis by allowing hierarchical, block-structured dataflow graphs with block-level parallelism. Program path probabilities are taken into account; and both high-level synthesis and design-space exploration are addressed. lNTRODUCTlONHigh-level synthesis is the automatic compilation of a highlevel behavioral description of a digital system into a register transfer structure trading off serial / parallel alternatives. Several major tasks are usually distinguished: high-level program transformations, scheduling, and the allocation of modules, registers and interconnections. The behavioral description is compiled into a graph representation, and high-level program transformations, such as common subexpression elimination. are done. Based on the underlying micro-architecture model, the datapath is synthesized, and the required control is derived as a symbolic state machine. Scheduling irs the assignment of operations to control steps or cycles. Module allocation consists of assigning operations to hardware module instances, and includes the subtask of module type selection, which consists of assigning operations to module types. Register allocation establishes the correspondence between values and registers or memory. Interconnect allocution specifies data transfer by multiplexers and busses. The scheduling methods, constraint formulations, cost functions, and sequence and interdependence of scheduling and allocation tasks differ among synthesis approaches (see [McPC88]). Both force-directed scheduling algorithms (FDS and FDLS) of the HAL system [PaKn89] aim at an allocation achieving high utilization of hardware modules. Within the CADDY system [KNRR88], operations are scheduled based on an estimation of the execution-time delay of the possible allocations. A problem with doing scheduling before allocation is the lack of knowledge about the datapath topology, which is crucial for realistic estimation of wiring costs. Within the MAHA system [PaPM86] scheduling and allocation are done simultaneously. Once the critical path operations are scheduled, the remaining operations are scheduled based on their measures of freedom. A more global solution is attempted by the simulated annealing approach of [DeNe89] in which the different allocation tasks are understood as a placement problem, scheduling being only a subproblem. This approach seems the most symmetric and global. but does not allow for user interaction and short turn-around times. The BUD-DAA system [McFa86], which inspired our work, can he viewed as allocation aiming at a favorable schedule, and does design partitioning using a hierarchical clustering method based on a metric of distance between operations. Clustering can also be done just before logic synthesis [C&87] or just before module allocation [DLTh89]. We extend the approach of the BUD-DAA system in two ways. First, we introduce a schedule distance to weig...