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Timing diagrams with data and timing annotations are introduced as a language for specifying interface circuits. In this paper we describe how to generate VHDL from timing diagrams in order to get a hardware implementation or simply to get VHDL code for stimuli to be used in a test bench. By giving timing diagrams a formal semantics in terms of T-LO'I'OS, we can apply optimizing correctness-preserving transformation steps. In order to produce good VHlDL code on the way to a hardware implementation it is of great importance to introduce structures into the final description that are not automatically derivable from a given Specification. The designer is rather asked to assist in introducing a structure by applying a Ibottomup interactive synthesis procedure.

Given U controller specgcution, it is attrucrive to synthesize alternu five implementdons .following different design pardigms such as synchronous, usynchronous or mixed-mode techniques. Present upprouches to uutoriuitic top-down as well us to interactive bottom-up synthesis ,fail to support multiple parudigms, because they w e based on internal (formal) models, which ure not generul enough. This puper introduces process culculi to serve us a husis .for multi-purudigm synthesis from the sume high-level specGCation interfuce, notably timing diagrums. Due to their .form1 manifestation. every synthesis step is vergable. This leads to guaranteed correct irr~plerrwntations. INTRODUCTIONThe task of a controller consists of the synchronization of independently designed subsystems to realize a desired overall system behavior. Therefore the controller has to assure the proper intertwining of commanding and responding signals of all involved submodules without violating their timing constraints. What induces complexity is that all submodule communication can happen concurrently. A typical controller instance is represented by a cotrununication interface. The UO-behavior of the communicating partners, usually referenced to as their communication protocol, is specified wrt. causality, timing and logic levels and is mostly given as a collection of timing diagrams. The controller mediates between these behaviors and, hence, can be thought of as converting one protocol into the other. Clearly, the implementation of such a controller can follow different design paradigms, each favorable for different aspects. Subrahmanyam [ 111 advocates the idea of a CAD system, which synthesizes for a single abstract specification some alternative implementations following different design styles "to enable a designer to synergistically exploit the advantages of both the synchronous and asynchronous (self-timed) design styles . . . and to support experhnenhtion with . . . implementation strategies". This paper presents a novel high-level controller synthesis approach, which supports different unplementation paradigms, derived from one common specification given in terms of formalized timing diagrams.Timing diagrams are a quite familiar way for users to specify control processes. They are more abstract than state charts, which handle the signal timing more restrictive than necessary. Timing diagrams as a specification interface are already used in present approaches to controller synthesis. Borriello and Katz [3] transform timing diagrams into event graphs that model the timed ordering of signal edges and can be compiled directly into skeleton circuits, which may need heuristic-based modifications to satisfy timing constraints. Event graphs are special graphs with no underlying general formalism. In contrast, Fujita and Fujisawa [6] describe a high-level-synthesis method for synchronous controllers formally based on Temporal Logic. They use timing diagrams as specification input, from which a rule based generator derives temporal logic formulas...