“…The industrial interest in the application of formal methods to the design of complex ASICs is noteworthy. Design methodologies have been proposed ( [8], [15], [16], [17], [18], [23], [24]) and commercial tools are now available ( [9], [19]) to partially support the design practice with the power of formal reasoning. In this paper we focus on the application of high-level formal based synthesis ( [3], [14]), that aims at improving the management of the first phases of the design process, addressing both the specification phase and the following partitioning steps at the architectural and/or scheduling/allocation levels.…”