Introducing structure into behavioural descriptions obtained from timing diagram specifications

Tiedemann, Wolf-Dieter; Grobe, Christian; Grass, Werner

doi:10.1016/0165-6074(93)90198-t

Cited by 11 publications

(4 citation statements)

References 7 publications

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“…As part of the Format project [Tiedeman et al 1993] behavior-preserving transformations are used to synthesize behavioral specifications of communication dominated hardware into structural VHDL. Specifications are defined by means of timing diagrams which are translated to T-LOTOS.…”

Section: Related Workmentioning

confidence: 99%

From VHDL to efficient and first-time-right designs

Middelhoek

Sunitha

1996

ACM Trans. Des. Autom. Electron. Syst.

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In this article we provide a practical transformational approach to the synthesis of correct synchronous digital hardware designs from high-level specifications. We do this while taking into account the complete life cycle of a design from early prototype to full custom implementation. Besides time-to-market, both flexibility with respect to target architecture and efficiency issues are addressed by the methodology. The utilization of user-selected behaviorpreserving transformation steps ensures first-time-right designs while exploiting the experience, flexibility, and creativity of the designer.To ensure that design transformations are indeed behavior-preserving a novel mechanized approach to the specification and verification of design transformations on control data flow graphs which is independent of a specific behavioral model or graph size has been developed.As a demonstration of an industrial application we use a video processing algorithm needed for the conversion from a line-interlaced to progressively scanned video format. Both a video signal processor-based prototype implementation as well as a very efficient full custom implementation are developed starting from a single high-level behavioral specification of the algorithm in VHDL. Results are compared with those previously obtained using different tools and methodologies.

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Section: Related Workmentioning

confidence: 99%

From VHDL to efficient and first-time-right designs

Middelhoek

Sunitha

1996

ACM Trans. Des. Autom. Electron. Syst.

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“…In literature the problem of the technique to be used to describe a system has been widely discussed. Several specification methods have been proposed, including, FSM [11,12], Petri nets [13] and high level languages [5,14,15,16]. In this paper we use TTL (Templated T-LOTOS) as the specification language.…”

Section: Ttl: the Specification Languagementioning

confidence: 99%

“…TTL can be supported by a set of graphic tools which allow the designer to specify the behaviour of the system in a simple, immediate, familiar way. A possible approach would be like the one followed in [20], which illustrates a technique by which it is possible to go from specification of the system by time diagrams to a T-LOTOS specification; since TTL is a superset of T-LOTOS a similar tool can be built.…”

Section: Ttl: the Specification Languagementioning

confidence: 99%

Formal Codesign Methodology with Multistep Partitioning

1996

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A codesign methodology is proposed which is suitable for control-dominated systems but can also be extended to more complex ones. Its main purpose is to optimize the trade-off between hardware performance and software reprogrammability and reconfigurability. The methodology proposed intends to cover the development of the whole system. It deals in greater detail with the steps that can be made without the need for any particular assumption regarding the target architecture. These steps concern splitting up the specification of the system into a set of individually synthesizable elements, and then grouping them for the subsequent mapping stage. In order to decrease the complexity of each partitioning attempt, a two step algorithm is proposed, thus permitting a wide exploration of possible solutions. The methodology is based on the TTL language, an extension of the T-LOTOS Formal Description Technique which provides a large amount of operators as well as a formal basis. Finally, an example pointing out the complete design cycle, excepting the allocation stage is provided.

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“…Techniques presented in [14 and 191 can be used for changing the implementation suggestion. [26], ESPRIT/FORMAT [27]) however most of them are restricted to optimizations at a single abstraction level (algebraic, loop, common subexpression ehmination, retiming and scheduling transformations), some, such as GATE and HYPER, include limited refinement by means of strength reduction transformations. Although such approaches have proven to be useful in many cases (examples include optimizing resource utilization, critical path minimization, power reduction, increased testability, all within the context of HYPER, memory reduction [18], and scheduling [23,24]), we found that they are too limited for full scale transformational design.…”

Section: Implementation Suggestionmentioning

confidence: 99%

Arbitrary hardware software trade-offs

Middelhoek

Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path From Specification to Prototype

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This paper discusses a novel transformation based design methodology and its use in the design of complex programmable VLSI systems. During the life cycl'e of a complex system the optimal trade-off between, partially, implementing in hardware or sofnvare is changing. This is due to varying system requirements (short time-tomarket, low-cost, low-power etc.) and improving device technology. The proposed methodology allows such redesigns to be made, using different hardware-software trade-offs, in a guaranteed correct way.

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Introducing structure into behavioural descriptions obtained from timing diagram specifications

Cited by 11 publications

References 7 publications

From VHDL to efficient and first-time-right designs

From VHDL to efficient and first-time-right designs

Formal Codesign Methodology with Multistep Partitioning

Arbitrary hardware software trade-offs

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