A Formal Definition of an Abstract VHDL’93 Simulator by EA-Machines

A Formal Behavioral Semantics for TestML

“…For hardware description languages, ASM was applied to define the different behavioral semantics of their respective simulators. In 1995 the simulation semantics of VHDL'93 was also introduced by Abstract State Machines in [13] as a complementary precise, formal, but yet readable, documentation to capture the relevant principles of non-trivial interaction of the user defined VHDL processes and the VHDL simulation kernel. Later, the ASM approach was also applied to define the complete execution semantics of SystemC in [14], SpecC in [15] and SystemVerilog in [16].…”

Generating test cases for marine safety and security scenarios: a composition framework

“…Building on common and widely used concepts from discrete mathematics and computational logic, it combines abstract states with transition systems. Abstract state machines are known for their semantic foundations for architectures, languages, and protocols, including some of the most prominent ones such as Java, SDL, and VHDL [15][16][17][18][19][20].…”

Voice over IP: Correct hardware/software co-design

“…In the past few years there have been several successful hardware verification efforts, some using model-checking techniques [11,12,13,14] others use the HOL system [3] and others based on functional calculi [10] and Abstract State Machines [7,8,9], . Once both implementation and specification are given, these techniques explore the correspondence between the two representations.…”