A forward body bias generator for digital CMOS circuits with supply voltage scaling

Meijer, Maurice; Gyvez, José Pineda de; Kup, B.M.J.; Uden, Bert van; Bastiaansen, P. A. M.; Lammers, M.; Vertregt, M.

doi:10.1109/iscas.2010.5537129

Cited by 25 publications

(11 citation statements)

References 10 publications

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“…Body Bias voltages are distributed classically to the standard Nwell and Pwell taps through the Power and Ground grid (Fig.4), as is done in Bulk implementations [6], [7]. Nwell and Pwell ties are spaced like they were in Bulk implementations.…”

Section: Generation and Distribution Of Body Voltagesmentioning

confidence: 99%

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Flatresse¹

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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Planar UTBB FD-SOI technology is an opportunity for energy efficient SOCs in deeply scaled technologies. Thanks to its excellent responsiveness to power management design techniques, this technology brings a significant improvement in terms of performance and power savings. The unique features offered by this technology at process and design levels enable a differentiation in terms of flexibility, cost and energy efficiency with respect to any process available on the market. KeywordsUTBB FD-SOI; multi-V T ; energy efficiency; low voltage; ultra wide voltage range; process compensation; body biasing, SOC.

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Section: Generation and Distribution Of Body Voltagesmentioning

confidence: 99%

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Flatresse¹

2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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“…Dynamic FBB requires a voltage generator circuit to generate the N-well and P-well bias voltages. A 90-nm LP-CMOS solution has been presented in [20]. This FBB generator occupies 0.03 mm for driving digital circuits of 1 mm , translating into 3% area overhead.…”

Section: Physical Design Aspects and Body Bias Generationmentioning

confidence: 99%

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

Meijer

Gyvez

2012

IEEE Trans. VLSI Syst.

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Abstract-Worst-case design uses extreme process corner conditions which rarely occur. This limits maximum speed specifications and costs additional power due to area over-dimensioning during synthesis. We present a new design synthesis strategy for digital CMOS circuits that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. An in-depth analysis of the body-bias-driven design theory is provided. It is complemented by an algorithm that enables fast reconstruction of the area-clock period tradeoff curve of the design. We validated these new concepts through industrial processor designs in 90-nm low-power CMOS. For standard-th implementations, we observed performance-per-area improvements up to 40%, area and leakage reductions up to 30%, and dynamic power savings of up to 10% without performance penalties as a benefit from our proposed body-bias-driven design strategy. The benefits are larger for high-th implementations. In this case, we observed performance-per-area improvements up to 90%, area and leakage reductions up to 40%, and dynamic power savings of up to 25% without performance penalties.

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“…The first term, i.e., , is a linear function of the elements of and is therefore convex. Based on Lemma 4.1, the second term in (12) is convex iff (13) To show this, note that we can write (14) Since the leakage power dissipation values are always positive,…”

Section: Lemma 42: the Objective Function In (12) Is A Convex Functimentioning

confidence: 99%

“…Kulkarni et al [12] evaluated the overheads for gate-level partitioning of a circuit with roughly 15 000 gates into three body-bias islands to be only 3.1%, although the overhead increases with an increasing number of islands. Multiple body-bias islands also require multiple body-bias voltage generators and supply networks for which a number of area efficient solutions have recently been proposed [14], [21].…”

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confidence: 99%

System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands

Garg

Marculescu

2012

IEEE Trans. VLSI Syst.

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Adaptive body biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of "body-bias islands," each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation technique to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate-and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics-in our case the execution deadlines. Experimental results show the efficacy of the proposed methodology; we demonstrate up to 40% and 60% reduction in the mean and standard deviation of leakage power dissipation respectively, compared to a baseline system without ABB. Furthermore, the proposed design-time partitioning is, on average, 38 faster than a previously proposed Monte Carlo-based technique, while providing similar reductions in leakage power dissipation.Index Terms-Adaptive body-bias (ABB), leakage power dissipation, power management, process variations.

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A forward body bias generator for digital CMOS circuits with supply voltage scaling

Cited by 25 publications

References 10 publications

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits

System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands

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