Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Flatresse, Philippe

doi:10.1145/2627369.2631640

Cited by 11 publications

(4 citation statements)

References 7 publications

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“…The major advantage of modern FD-SOI processes is the introduction of a fourth terminal -the back gate -to the MOS transistor. This terminal allows controlling the threshold voltage by about 85 mV/V when changing the back gate voltage [2,3]. Here, it must be considered which well option is to be used.…”

Section: Body Biasing Fundamentalsmentioning

confidence: 99%

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Body biasing for analog design: Practical experiences in 22 nm FD-SOI

Rao

Prautsch

Shrivastava

et al. 2017

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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This paper presents the practical application of body biasing control of ultra-deep submicron FD-SOI technologies for analog and mixed-signal designs. The body biasing control is dedicated for dynamic control of the tradeoff between speed vs. power consumption for advanced digital circuits. However, in this work we focus on trading-off and improvement of analog circuit performances. Three different circuits were explored and designed: an all CMOS bandgap reference, a 500 MSps current-steering DAC, and a 12-bit sigma-delta modulator. All designs were verified and realized in Globalfoundries 22 nm FD-SOI technology

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Section: Body Biasing Fundamentalsmentioning

confidence: 99%

“…RVT and LVT devices trade-off power consumption and maximum frequency. RVT devices reduce leakage while LVT devices show more leakage and allow higher operation frequencies due to more driving current [2,4]. So, it is an essential and early design decision which transistor type is to be used.…”

Section: Body Biasing Fundamentalsmentioning

confidence: 99%

Body biasing for analog design: Practical experiences in 22 nm FD-SOI

Rao

Prautsch

Shrivastava

et al. 2017

2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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“…However, in the selected FD-SOI technology, separation of V T regions requires significant area overhead. Therefore, for leakage reduction, low-leakage poly-biased latches were used to implement the storage latches [Flatresse 2014], whereas minimum-length gates were used for the output multiplexer.…”

Section: Performance Comparisonmentioning

confidence: 99%

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Teman

Rossi

Meinerzhagen

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

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Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors through memory generators, targeted at rather generic design specifications. As an alternative, standard cell memories (SCMs) can be defined, synthesized, and placed and routed as an integral part of a given digital system, providing complete design flexibility, good energy efficiency, low-voltage operation, and even area efficiency for small memory blocks. Yet implementing an SCM block with a standard digital flow often fails to exploit the distinct and regular structure of such an array, leaving room for optimization. In this article, we present a design methodology for optimizing the physical implementation of SCM macros as part of the standard design flow. This methodology introduces controlled placement, leading to a structured, noncongested layout with close to 100% placement utilization, resulting in a smaller silicon footprint, reduced wire length, and lower power consumption compared to SCMs without controlled placement. This methodology is demonstrated on SCM macros of various sizes and aspect ratios in a state-of-the-art 28nm fully depleted silicon-on-insulator technology, and compared with equivalent macros designed with the noncontrolled, standard flow, as well as with foundry-supplied SRAM macros. The controlled SCMs provide an average 25% reduction in area as compared to noncontrolled implementations while achieving a smaller size than SRAM macros of up to 1Kbyte. Power and performance comparisons of controlled SCM blocks of a commonly found 256 × 32 (1 Kbyte) memory with foundry-provided SRAMs show greater than 65% and 10% reduction in read and write power, respectively, while providing faster access than their SRAM counterparts, despite being of an aspect ratio that is typically unfavorable for SCMs. In addition, the SCM blocks function correctly with a supply voltage as low as 0.3V, well below the lower limit of even the SRAM macros optimized for low-voltage operation. The controlled placement methodology is applied within a full-chip physical implementation flow of an OpenRISC-based test chip, providing more than 50% power reduction compared to equivalently sized compiled SRAMs under a benchmark application.

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“…However, several recent works [3][4][5][6][7][8][9] have demonstrated the implementation of a novel SOI-based technology labeled ultra-thin body and buried oxide (UTBB), in which fully depleted (FD) devices are fabricated on SOI wafers that present extremely thin silicon and BOX thicknesses (t Si and t box , respectively) and undoped (or not intentionally doped) channel region. These devices have been developed to compete with the multigate architecture for extremely scaled devices and have shown promising electrical performance also for analog applications [10][11][12] required in purely analog or mixed analog-digital systems.…”

Section: Introductionmentioning

confidence: 99%

Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

Doria¹,

Flandre²,

Trevisoli³

et al. 2017

Semicond. Sci. Technol.

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This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and UTBB fully depleted (FD) SOI MOSFETs to the structures and has shown that a voltage gain improvement of about 7 dB is obtained when a forward back bias is applied to the drain-sided transistor of standard FD devices-based structure. In the case of UTBB transistors, an improvement larger than 5 dB of the output voltage gain is shown depending on the back bias applied to both n-or p-type devices. Finally, it is shown that the mirroring precision of current mirrors composed by SC structures can be more than 20% better than the one composed by single devices and the improvement is better when adequate back bias is applied.

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Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs

Cited by 11 publications

References 7 publications

Body biasing for analog design: Practical experiences in 22 nm FD-SOI

Body biasing for analog design: Practical experiences in 22 nm FD-SOI

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

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