Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures

Abstract

This work demonstrates that active back biasing can improve significantly the analog performance of two-transistors self-cascode structures. The study was performed by applying both standard and UTBB fully depleted (FD) SOI MOSFETs to the structures and has shown that a voltage gain improvement of about 7 dB is obtained when a forward back bias is applied to the drain-sided transistor of standard FD devices-based structure. In the case of UTBB transistors, an improvement larger than 5 dB of the output voltage gain is shown depending on the back bias applied to both n-or p-type devices. Finally, it is shown that the mirroring precision of current mirrors composed by SC structures can be more than 20% better than the one composed by single devices and the improvement is better when adequate back bias is applied.

Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors

“…In this case, VSUB refers to voltage applied to the substrate of the nMOS device whereas the substrate of the pMOS receives the opposite voltage, i.e., if -2 V is applied to the substrate of the nMOS, 2 V is applied to the pMOS. This configuration was adopted based on previous results for CMOS circuits compounded by UTBB devices [25]. It is worth to mention that for VSUB = 0 V, the substrates of both devices are tied to the ground.…”

Analysis of Current Mirrors with Asymmetric Self-Cascode Association of SOI MOSFETs through SPICE Simulations

“…The reduced threshold voltage of MD forces it to work in saturation, absorbing part of the voltage bias applied to the drain of the composite transistor structure. This structure has been reported to provide several advantages from analog perspective, at device level, such as larger current drain, transconductance and breakdown voltage and reduced output conductance in comparison to S-SC and single transistors with similar dimensions [10,11,12,13].…”