A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers

Esfahani, F.; Basedau, P.; Ryter, R.; Becker, R.

doi:10.1109/vlsic.2003.1221166

Cited by 10 publications

(3 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Single loop sigma delta architecture often use of several topologies for loop filter, such as chain of integrators with weighted feedforward summation (CIFF) [6], and chain of integrators with distributed feedback (CIFB) [7], resulting in stability and realization considered transfer functions. CIFF topology has several benefits in compared to CIFB.…”

Section: Basic Principle Of Proposed Complex Filtermentioning

confidence: 99%

A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver

Ahmadpoor¹,

Farshidi²

2012

View full text Add to dashboard Cite

In this paper, new complex band pass filter architecture for continuous time complex band pass sigma delta modulator is presented. In continuation of paper the modulator is designed for GPS and Galileo receiver. This modulator was simulated in standard 0.18 µm CMOS TSMC technology and has bandwidth of 2 MHz and 4 MHz for GPS and Galileo centered in 4.092 MHz. The dynamic range (DR) is 56.5/49 dB (GPS/Galileo) at sampling rate of 125 MHz. The modulator has power consumption of 4.1 mw with 3 V supply voltage.

show abstract

Section: Basic Principle Of Proposed Complex Filtermentioning

confidence: 99%

A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver

Ahmadpoor¹,

Farshidi²

2012

View full text Add to dashboard Cite

show abstract

“…Due to these advantages, the mixed-signal community has been actively researching CT ADC structures [12]- [15], [19]- [21], [26]- [31]. Our contribution to this effort is to highlight the benefits of using a VCO-based quantizer to implement the multi-bit quantizer within the CT structure.…”

Section: Introductionmentioning

confidence: 99%

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS

Park

Perrott²

2009

IEEE J. Solid-State Circuits

193

View full text Add to dashboard Cite

The use of a VCO-based integrator and quantizer within a continuous-time (CT) 16 analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 m CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm 2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

show abstract

“…13 depicts the layout of the A/D-converter-core showing an attractively small size of 260 µm × 305 µm = 0.079 mm 2 including the voltage reference buffer. Most of the silicon area needs to be spent for arrays of linear unit-capacitors of the loopfilter whereas the consumed area by resistors and active MOS-devices play a minor role.…”

mentioning

confidence: 99%

Delta-Sigma A/D-Converters

Gaggl¹

2013

Springer Series in Advanced Microelectronics

View full text Add to dashboard Cite

The Springer Series in Advanced Microelectronics provides systematic information on all the topics relevant for the design, processing, and manufacturing of microelectronic devices. The books, each prepared by leading researchers or engineers in their fields, cover the basic and advanced aspects of topics such as wafer processing, materials, device design, device technologies, circuit design, VLSI implementation, and subsystem technology. The series forms a bridge between physics and engineering and the volumes will appeal to practicing engineers as well as research scientists.

show abstract

A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers

Cited by 10 publications

References 8 publications

A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver

A New Approach to Complex Bandpass Sigma Delta Modulator Design for GPS/Galileo Receiver

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$m CMOS

Delta-Sigma A/D-Converters

Contact Info

Product

Resources

About