A FPGA architecture for real-time processing of variable-length FFTS

Langemeyer, Stefan; Pirsch, P.; Blume, Holger

doi:10.1109/icassp.2011.5946829

Cited by 9 publications

(5 citation statements)

References 6 publications

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“…x 3 X[15] X [13] X [14] X [12] Our proposed output reorder block consists of 8-RAM blocks and this 8 RAM blocks behave such as single RAM block with RAM addressing unit. The main reason for using 8 RAM blocks in this way is that the proposed architecture is designed for a 4-parallel sample structure.…”

Section: Reorder Circuitmentioning

confidence: 99%

“…First of all, if we examine the addressing of 16-point FFT results during writing and reading, it is sufficient to use a 4-bit address for 16 data. 16-point FFT outputs, X[0], X [8], X [4], X [12], X [2], X [10], X [6], X [14], X [1], x [9], X [5], X [13], X [3], X [11], X [7], X [15] are written to addresses 0, 1, 2, 3,4,5,6,7,8,9,10,11,12,13,14 Output data of X [25] are written to waddr "10011" in case of 32-point FFT size. Address waddr is decoded as {waddr(4), waddr(3)} = "10", {waddr(1), waddr(2)} = "10", waddr(0) = "1" and points address "10" of RAM-1 in the main RAM group "10".…”

Section: Reorder Circuitmentioning

confidence: 99%

See 1 more Smart Citation

HC-FFT: highly configurable and eﬀicient FFT implementation on FPGA

ERGÜL¹,

Uğurdağ²,

DAVUTOĞLU³

2021

Turk J Elec Eng & Comp Sci

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FFT is one of the basic building blocks in many applications such as sensors, radars, communications. For some applications, e.g., real-time spectral monitoring and analysis, FFT needs to be "run-time configurable" so that the system is real-time. When examining the previous work on configurable real-time (FPGA-based) FFT implementations, we see that the degree of configurability is less than what is desired. In this paper, a new FFT architecture is proposed, which has a high degree of run-time configurability and yet does not compromise area or throughput. The configurable parameters of this design are the number of FFT points (up to 64K), forward versus inverse mode, output order (natural or bit-reversed), and the number of streams (up to 4). The proposed FFT architecture (HC-FFT) is designed using a parallel and pipelined radix-2 multipath delay commutator (MDC) FFT structure. HC-FFT was implemented on a Xilinx Kintex Ultrascale FPGA and was verified against the Xilinx FFT IP. Besides its high degree of run-time configurability, HC-FFT is quite efficient and offers a very high throughput of 87 Gbps with a quite reasonable area.

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Section: Reorder Circuitmentioning

confidence: 99%

Section: Reorder Circuitmentioning

confidence: 99%

HC-FFT: highly configurable and eﬀicient FFT implementation on FPGA

ERGÜL¹,

Uğurdağ²,

DAVUTOĞLU³

2021

Turk J Elec Eng & Comp Sci

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“…FFT processors for the RDA typically support a fixed length, making it challenging to apply this algorithm in various SAR applications. Therefore, a variable-length FFT processor is required [36]. Many FFT algorithms are available, including radix-2, radix-4, radix-8, radix-2 2 , radix-2 3 , and mixed-radix.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

et al. 2021

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In this paper, we propose a range-Doppler algorithm (RDA)-based synthetic aperture radar (SAR) processor for real-time SAR imaging and present FPGA-based implementation results. The processing steps for the RDA include range compression, range cell migration correction (RCMC), and azimuth compression. A matched filtering unit (MFU) and an RCMC processing unit (RPU) are required for real-time processing. Therefore, the proposed RDA-based SAR processor contains an MFU that uses the mixed-radix multi-path delay commutator (MRMDC) FFT and an RPU. The MFU reduces the memory requirements by applying a decimation-in-frequency (DIF) FFT and decimation-in-time (DIT) IFFT. The RPU provides a variable tap size and variable interpolation kernel. In addition, the MFU and RPU are designed to enable parallel processing of four 32-bit which are transferred via a 128-bit AXI bus. The proposed RDA-based SAR processor was designed using Verilog-HDL and implemented in a Xilinx UltraScale+ MPSoC FPGA device. After comparing the execution time taken by the proposed SAR processor with that taken by an ARM cortex-A53 microprocessor, we observed a 85-fold speedup for a 2048 × 2048 pixel image. A performance evaluation based on related studies indicated that the proposed processor achieved an execution time that was approximately 6.5 times less than those of previous FPGA implementations of RDA processors.

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“…FPGA implementation of pipelined FFT architectures are proposed in [12]. several other parallel pipeline designs in recent years proposed in [13], [14], [15].…”

Section: Introductionmentioning

confidence: 99%

Two Parallel Pipelined FFT Architecture After Third Stage for Low Complexity and Latency

G¹,

Krishna²,

Kotipalli³

2019

IJITEE

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Complexity is the major issue in the development of pipelined Fast Fourier Transform (FFT) structure. A novel parallel pipelined FFT design constructed for low complexity and Latency. The proposed structure efficiently uses pipeline and parallel pipeline in the design. The first three stages of the structure follow the pipelining and from fourth stage there are two parallel paths simultaneously compute four complex additions, the first three single path stages that reduces complexity, parallel pipeline stages at the end of structure also reduces the Latency. The proposed structure is an optimized solution to reduce the trade-off between Latency and complexity. The comparative performance of the proposed structure with several other existing structures shows that it has Low latency with small cost of hardware

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A FPGA architecture for real-time processing of variable-length FFTS

Cited by 9 publications

References 6 publications

HC-FFT: highly configurable and eﬀicient FFT implementation on FPGA

HC-FFT: highly configurable and eﬀicient FFT implementation on FPGA

FPGA Implementation of the Range-Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging

Two Parallel Pipelined FFT Architecture After Third Stage for Low Complexity and Latency

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