A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs

Lee, S.Y.; Jung, Dong-Hoon; Song, Y. J.; Koo, Bonjae; Park, S.O.; Cho, H.J.; Oh, Seungjae; Hwang, Dongwon; Lee, S.I.; Lee, J.K.; Park, Y.S.; Jung, Insoo; Kim, Kinam

doi:10.1109/vlsit.1999.799383

Cited by 8 publications

(2 citation statements)

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“…[ 18 ] Although easy to process at a low cost, this cell structure occupies a large cell area because the ferroelectric capacitor is formed in a separate place that is offset from the transistor. The introduction of a stacked cell structure using capacitor‐over‐bitline technology, [ 19 ] in which the capacitor is located above the transistor, resulted in a significant reduction in FeRAM cell size. [ 15 ] Further FeRAM miniaturization was achieved using chain‐cell structure technology.…”

Section: History Of Conventional Ferroelectric Memoriesmentioning

confidence: 99%

Revival of Ferroelectric Memories Based on Emerging Fluorite‐Structured Ferroelectrics

et al. 2023

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Over the last few decades, the research on ferroelectric memories has been limited due to their dimensional scalability and incompatibility with complementary metal‐oxide‐semiconductor (CMOS) technology. The discovery of ferroelectricity in fluorite‐structured oxides revived interest in the research on ferroelectric memories, by inducing nanoscale nonvolatility in state‐of‐the‐art gate insulators by minute doping and thermal treatment. The potential of this approach has been demonstrated by the fabrication of sub‐30 nm electronic devices. Nonetheless, to realize practical applications, various technical limitations, such as insufficient reliability including endurance, retention, and imprint, as well as large device‐to‐device‐variation, require urgent solutions. Furthermore, such limitations should be considered based on targeting devices as well as applications. Various types of ferroelectric memories including ferroelectric random‐access‐memory, ferroelectric field‐effect‐transistor, and ferroelectric tunnel junction should be considered for classical nonvolatile memories as well as emerging neuromorphic computing and processing‐in‐memory. Therefore, from the viewpoint of materials science, this review covers the recent research focusing on ferroelectric memories from the history of conventional approaches to future prospects.

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Section: History Of Conventional Ferroelectric Memoriesmentioning

confidence: 99%

Revival of Ferroelectric Memories Based on Emerging Fluorite‐Structured Ferroelectrics

et al. 2023

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“…Recently, it was announced that a 4 Mb FRAM was developed by using one transistor and one capacitor (1T/1C) cell scheme and capacitor over bit line (COB) structure [1]. In the 4 Mb FRAM device, Pb(Zr Ti )O (PZT) films are prepared on polysilicon-plugged substrate by sol-gel technique.…”

Section: Introductionmentioning

confidence: 99%

Novel capacitor process using diffusion barrier rounded by Si/sub 3/N/sub 4/ spacer for high density FRAM device

Koo

Song

Lee

et al. 2000

IEEE Electron Device Lett.

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A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si 3 N 4 spacer (BRS) scheme. Using this process, it is possible to eliminate an undesired barrier etching damage, which is a major role in degrading ferroelectric properties. The novel capacitor process was generated by etching an Ir barrier layer and rounding the barrier by Si 3 N 4 spacer before preparing Pb(Zr 1 Ti )O 3 (PZT) films. It was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si 3 N 4 spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and polysilicon plug after full integration was monitored below 700 per contact with contact size 0.6 0.6 ( m 2 ). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr 1 Ti )O 3 (PZT) capacitor exhibited well-saturated Q-V curve. The fully processed novel capacitor having 1.2 1.2 ( m 2 ) effective area displayed remnant polarization of 14 ( C/cm 2 ) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125 C. Same state retention (Qss) was stable with time up to 100 h while opposite state retention (Qos) showed a log-linear decay rate at 125 C thermal stress. Index Terms-FRAM, Pb(Zr 1 Ti )O 3 , sol-gel spin coating.

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Ferroelectric RAMs

Emerging Memories

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A FRAM technology using 1T1C and triple metal layers for high performance and high density FRAMs

Cited by 8 publications

References 1 publication

Revival of Ferroelectric Memories Based on Emerging Fluorite‐Structured Ferroelectrics

Revival of Ferroelectric Memories Based on Emerging Fluorite‐Structured Ferroelectrics

Novel capacitor process using diffusion barrier rounded by Si/sub 3/N/sub 4/ spacer for high density FRAM device

Ferroelectric RAMs

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