A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations

Abstract-Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. Using transition delay test, this paper analyzes the behavior of resistive bridge defect under the influence of process variation. The effect of process variation is incorporated by using three transistor parameters: gate length (L), threshold voltage (V th ) and effective mobility (µ ef f ), where each follows Gaussian distribution. Through HSPICE simulations using a 65-nm gate library, this paper brings the following two contributions: firstly, it analyzes the delay behavior of bridge defect using all three transition delay classes to determine the most effective class of transition test that achieves maximum coverage in the presence of process variation. Secondly, recent research has shown that lowvoltage testing improves detectability of bridge fault; this work compares bridge resistance coverage using logic test and delay test at multiple voltage settings to identify the best voltage setting and test type for detecting resistive bridge defects.Index Terms-Resistive bridge defects, transition delay test, process variation, logic test, low voltage test.

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Critical Paths Selection and Test Cost Reduction Considering Process Variations

Chen

Tehranipoor

2013

2013 22nd Asian Test Symposium

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A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations

Cited by 16 publications

References 14 publications

Full exploitation of process variation space for continuous delivery of optimal delay test quality

Full exploitation of process variation space for continuous delivery of optimal delay test quality

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation

Critical Paths Selection and Test Cost Reduction Considering Process Variations

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