A full Nyquist 15 MS/s 8-b differential switched-current A/D converter

Bracey, M.; Redman-White, W.; Richardson, J.; Hughes, J.B.

doi:10.1109/4.508207

Cited by 27 publications

(13 citation statements)

References 13 publications

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“…To achieve a positive CINJ, the switch is a PMOS. Similar to (8) and (9), the CINJ current offset can be derived (16) where (17) where is the threshold voltage of PMOS. The FIMP current offset is similarly derived as (7) (18) where is the transistor parameter for M2.…”

Section: B S I Mdacmentioning

confidence: 99%

“…1 shows the measurements of major SI pipeline/cyclic ADCs, the sample/hold stages reported so far [10]- [20] of which [10]- [15] are single-ended designs. In [16] and [17], differential pipeline ADCs are discussed. In [18]- [20], fully differential designs are presented.…”

mentioning

confidence: 99%

“…Performance-related equations are of great value because good equations can always be combined with simulation routines to form a combined CAD tool that can efficiently guide the adaptation engine to reach a more accurate optimum in a relatively short duration [28]. Many methodologies have been developed for the design of SI circuits [17]- [33]. However, previous SI circuit design methodologies were mainly based on ideal behaviors of SI circuits or a simple quantitative analysis on nonidealities.…”

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confidence: 99%

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Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Yuan

2009

IEEE Trans. Circuits Syst. I

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Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-m CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution ( 12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.Index Terms-Analog computer-aided analysis and design (CAD), distortion, equation based, multiplying digital-to-analog converter (MDAC), noise, pipeline analog-to-digital converters (ADCs), simulation based, switched capacitor, switched current.

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Section: B S I Mdacmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Yuan

2009

IEEE Trans. Circuits Syst. I

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“…Furthermore, high-speed operation is possible because the impedance of each node decreases. The high-speed operational capabilities of a current-based analog circuit have been previously demonstrated [3], [4]. The study referred to in [3] realized an 8-bit 15-MHz analog-to-digital (A/D) converter with a 5-V supply voltage by adopting the differential configuration of a switched-current circuit.…”

Section: Introductionmentioning

confidence: 99%

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s

Sugimoto

2001

IEEE J. Solid-State Circuits

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A new video-speed current-mode CMOS sampleand-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio ( ) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feedthrough, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6m MOS devices with normal threshold voltages ( th ) of +0.7 V (nMOS) and 0.7 V (pMOS).

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“…This avoids the need for precisely matched squarer circuits as is the case in some continuous time current multipliers [2]. This paper presents an alternative implementation by using the S I switched-current technique that has already been proven effective in filtering and converting applications [12]- [14]. One of the most important features of S I is that it allows to compensate for analog errors due to charge injection [10], [14], [15] as well as for those arising from the finite output impedance.…”

Section: Introductionmentioning

confidence: 99%

A Four Quadrant S2I Switched-Current Multiplier

Manganaro¹,

Gyvez²

1999

Cellular Neural Networks

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Abstract-The analysis, design, and implementation of a twostep current-sampling switched-current (S 2 I) multiplier is presented. The S 2 I technique has been employed to compensate analog errors due to charge injection as well as those arising from the finite output impedance. A thorough circuit analysis investigating the offset sources of the S 2 I cell and of the multiplier's nonlinearities sets up the platform to effectively design the multiplier and to avoid the use of feedback, or cascode techniques, to deal with channel modulation effects. The multiplier has been implemented using a 2-m n- A complete set of detailed experimental results is provided in the paper.

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A full Nyquist 15 MS/s 8-b differential switched-current A/D converter

Cited by 27 publications

References 13 publications

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s

A Four Quadrant S2I Switched-Current Multiplier

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