A Fully-Integrated 40–222 GHz InP HBT Distributed Amplifier

Cui

IEEE Microw. Wireless Tech. Lett.

et al. 2023

In this letter, we present the designs and development of a wideband, high output power quadruple-stacked heterojunction bipolar transistor (HBT) distributed amplifier (DA). In particular, the stacked HBT configuration can improve gain and output power while achieving a very wide bandwidth. To validate the proposed design concept, a quadruple-stacked HBT DA is designed in an indium phosphide (InP) process. The measurement results show an average gain of 16 dB from 7-115-GHz bandwidth with a maximum of 24-dBm saturated output power ( P sat ). To the best of the authors' knowledge, this is the first time quadruple-stacked HBT is used in a DA to achieve the highest output power compared with other published work in the same frequency range.

Section: Introductionmentioning

confidence: 99%

A 7–115-GHz Distributed Amplifier With 24-dBm Output Power Using Quadruple-Stacked HBT in InP

Cui

IEEE Microw. Wireless Tech. Lett.

et al. 2023

“…The traveling wave amplifier is common in broadband amplifier design, and is also known as a distributed amplifier (DA) [1][2][3][4][5][6]. The bandwidth, flatness, and output power of DAs are outstanding among broadband amplifiers.…”

Section: Introductionmentioning

confidence: 99%

“…The main limitation of DAs is that their maximum gain does not exceed the transistor, which limits their high-frequency applications because the transistor gain is inversely proportional to the operating frequency. The cascode structure is another commonly used topology for designing broadband amplifiers, and it is often used as a basic unit to form a DA to increase its gain [3]. Because of the narrow-band characteristics of the matching network, the common-emitter (CE) structure is considered unsuitable for broadband amplifier design [7][8][9].…”

Section: Introductionmentioning

confidence: 99%

A 56–161 GHz Common-Emitter Amplifier with 16.5 dB Gain Based on InP DHBT Process

Yanfei

et al. 2021

Electronics

This paper presents a broadband amplifier MMIC based on 0.5 µm InP double-heterojunction bipolar transistor (DHBT) technology. The proposed common-emitter amplifier contains five stages, and bias circuits are used in the matching network to obtain stable high gain in a broadband range. The measurement results demonstrate a peak gain of 19.5 dB at 146 GHz and a 3 dB bandwidth of 56–161 GHz (relative bandwidth of 96.8%). The saturation output power achieves 5.9 and 6.5 dBm at 94 and 140 GHz, respectively. The 1 dB compression output power is −4.7 dBm with an input power of −23 dBm at 94 GHz. The proposed amplifier has a compact chip size of 1.2 × 0.7 mm2, including DC and RF pads.

“…In general, most power amplifiers have been designed using III-V compound semiconductors because of the high linearity and breakdown voltage [1][2][3][4][5][6]. Additionally, given that the compound semiconductor process provides a through-hole via and thereby allows utilization of the back metal layer as a ground (GND) plane, a high quality GND level can be obtained using compound semiconductor based power amplifiers.…”

Section: Introductionmentioning

confidence: 99%

A Cmos Power Amplifier Using a Balun Embedded Driver Stage for Ieee 802.11N Wlan Applications

Son¹,

Yoo²,

Lee³

et al. 2019

PIER C

In this work, we propose a balun embedded driver stage to enhance the bandwidth and minimize the chip size of a differential CMOS power amplifier. By removing the passive input transformer, the bandwidth and chip size are improved. The proposed driver stage acts as an input balun as well as the driver stage for the power stage. The proposed driver is composed of a cascade connected PMOS, an inductor, and NMOS to generate the differential output signal. For the function of the input balun, the gate of the PMOS is connected to the drain of the NMOS. To verify the feasibility of the proposed balun embedded driver stage, we design a differential CMOS power amplifier for 5-GHz IEEE 802.11n WLAN applications. The designed power amplifier is fabricated using the 180-nm SOI RF CMOS process. The measured 3-dB bandwidth is approximately 2.5 GHz. The chip size of the fully integrated power amplifier, including input and output matching networks and test pads, is 0.885 mm 2. The measured maximum output power is 20.18 dBm with a PAE of 10.16%.