A GALS Infrastructure for a Massively Parallel Multiprocessor

Plana, Luis A.; Furber, Steve; Temple, Steve; Khan, Muhammad; Shi, Yebin; Wu, Jian; Yang, Shufan

doi:10.1109/mdt.2007.149

Cited by 112 publications

(90 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Every node of the network consists of a SpiNNaker Chip multiprocessor (CMP), which constitutes the basis of the system [18,19]. It comprises 20 processing cores and SDRAM memory.…”

Section: Spinnaker Architecturementioning

confidence: 99%

“…Its main task is to carry neuralevent packets between the processors that can be located on the same or different chips. Also, it transports system configurations and monitoring information [18,20]. The receiver of the data must be able to manage how long the sender keeps the data stable in order to complete a Delay-Insensitive communication.…”

Section: Spinnaker Architecturementioning

confidence: 99%

“…The receiver uses an acknowledgement to show that data has been accepted. The acknowledgement follows a return-to-zero protocol [18,20]. Figure 3 illustrates a SpiNNaker system composed of 25 SpiNNaker chips at a high level of abstraction.…”

Section: Spinnaker Architecturementioning

confidence: 99%

See 2 more Smart Citations

Modelling and Analysis Mobile Systems Using $$\pi $$ -calculus (EFCP)

Khomenko

Germanos

2015

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. Reference passing systems, like mobile and reconfigurable systems are common nowadays. The common feature of such systems is the possibility to form dynamic logical connections between the individual modules. However, such systems are very difficult to verify, as their logical structure is dynamic. Traditionally, decidable fragments of π-calculus, e.g. the well-known Finite Control Processes (FCP), are used for formal modelling of reference passing systems. Unfortunately, FCPs allow only 'global' concurrency between processes, and thus cannot naturally express scenarios involving 'local' concurrency inside a process, such as multicast. In this paper we propose Extended Finite Control Processes (EFCP), which are more convenient for practical modelling. Moreover, an almost linear translation of EFCPs to FCPs is developed, which enables efficient model checking of EFCPs.

show abstract

“…Every node of the network consists of a SpiNNaker Chip multiprocessor (CMP), which constitutes the basis of the system [18,19]. It comprises 20 processing cores and SDRAM memory.…”

Section: Spinnaker Architecturementioning

confidence: 99%

Section: Spinnaker Architecturementioning

confidence: 99%

See 1 more Smart Citation

Modelling and Analysis Mobile Systems Using $$\pi $$ -calculus (EFCP)

Khomenko

Germanos

2015

Lecture Notes in Computer Science

View full text Add to dashboard Cite

show abstract

“…The interconnect itself extends both on-chip and off-chip as the Communications Network-on-Chip (Comms NoC). Previous work ( [29,44]) describes the design of and configuration procedure for the Comms NoC. At the processor node, the communications controller receives and generates AER spikes, issuing an interrupt (i.e., an event) to the processor when a new packet arrives.…”

Section: Event-driven Processingmentioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

Self Cite

View full text Add to dashboard Cite

Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

show abstract

“…The SpiNNaker system [13] tries to overcome these issues by implementing a packet-switched network [14] that is used to carry out the communication between the processing elements that emulate the spiking neurons.…”

Section: Introductionmentioning

confidence: 99%