A GHz-class charge recovery logic

Sathe, Visvesh; Papaefthymiou, Marios C.; Ziesler, C.H.

doi:10.1109/lpe.2005.195492

Cited by 3 publications

(3 citation statements)

References 3 publications

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“…The input logic '0' value is 0.45 V and input logic '1' value is 1.4 V. Along with the energy values, the output logic values have been found to be 0.45 and 1.4 V corresponding to logic '0' and logic '1', respectively. From the Table 1, it is observed that for the adiabatic inverter, the simulated value of energy dissipation is comparable with the theoretical value obtained from (7).…”

Section: Simulation Of Invertersupporting

confidence: 74%

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Cascadable adiabatic logic circuits for low-power applications

Reddy¹,

Satyam

Kishore

2008

IET Circuits Devices Syst.

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There have been several strategies proposed to realise adiabatic circuits. Most of them require a clock signal and also its complement form. In this investigation, the authors we propose a family of adiabatic circuits, which consist of two branches and which enable control of charging and discharging of the capacitive load only by the input signal, work with single time varying supply and with no need of complementary inputs. A mathematical expression has been developed to explain the energy dissipation in our adiabatic inverter circuit. Measurements of energy drawn, recovered and dissipated have been carried out through simulation and, they are the same as obtained from the theoretical expression. In the proposed circuit, the input and output logic levels are approximately the same and can be used for building cascaded logic circuits. The energy saving in this family is to the tune of 50% compared with CMOS circuits constructed with similar circuit parameters, up to 250 MHZ. The authors have described the proposed inverter, NAND gates, NOR gates, adder circuits and JK flip-flop along with their simulation results. 518

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Section: Simulation Of Invertersupporting

confidence: 74%

“…Further, the load capacitor is charged irrespective of the inputs and, hence, it has limited cascadability and sometimes it also produces unwanted outputs. Sathe et al [7] proposed energy -efficient GHz-class chargerecovery logic, which needs the usage of additional power clocks and transistors to effect the boost operation.…”

Section: Introductionmentioning

confidence: 99%

Cascadable adiabatic logic circuits for low-power applications

Reddy¹,

Satyam

Kishore

2008

IET Circuits Devices Syst.

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“…There are other circuit level techniques including adiabatic logic [27], multivalued-logic [28], charge recovery clocking [29]. Due to limited space, we will not elaborate them.…”

Section: Reducing Capacity Of Clock Loadmentioning

confidence: 99%

Power optimization for VLSI circuits and systems

Zhao

Wang

Hang

2010

2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

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Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture level.

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A 1.1ghz charge-recovery logic

Sathe¹,

Chueh²,

Papaefthymio³

2006

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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Boost Logic is a charge-recovery circuit family capable of operating at GHz-class frequencies [1]. In this paper, the design and experimental validation of a 1.1GHz Boost Logic test chip is reported. The test chip is fabricated in a 0.13µm CMOS process with an integrated inductor and an on-chip clock generator. This chip is an implementation of a dynamic charge-recovery logic family operating successfully in the GHz regime. Previous charge-recovery circuit implementations with on-chip clock generators have been reported to operate at frequencies no greater than 130MHz [2,3,4]. In addition to fast operation, Boost Logic achieves high energy efficiency due to its (i) balanced clock load, (ii) decoupled logic evaluation and charge-recovery stages, and (ii) absence of diodes. This Boost Logic chip recovers 60% of the energy supplied to it at each clock cycle. Figure 21.5.1 shows a Boost Logic gate. It consists of a dual-rail logic stage that operates in tandem with a charge-recovering boost stage. The logic stage performs functional evaluation and is powered by a dc supply V C = V dd ' -V ss ' = V th , centered at V dd /2. The Boost stage then amplifies the potential difference between out and out to V dd . Figure 21.5.2 illustrates the operation of a Boost inverter. During the boost stage, the header and footer transistors of the logic stage are off, isolating the outputs from the logic rails. As φ(φ) transitions to V ss (V dd ), transistor M3 (M1) discharges (charges) the output node out (out). The output nodes track the power-clocks until their potential difference reaches V th , at which time all transistors in the boost stage are in cut-off and remain so during the subsequent logic stage. As φ falls below V ss ', logic evaluation begins, resolving the output nodes to a potential difference of nearly V th , and as φ crosses V dd ', the boost stage drives the output nodes to the full rail. By relying on resonance to drive the output nodes to a voltage difference V dd , the boost stage efficiently provides a high gate overdrive to fanout logic stages. Although V C = V th , all transistors conduct in the superthreshold linear region due to this high gate overdrive.Fabricated in a 0.13µm 8M (copper, 2 thick) 1.2V CMOS process, this test chip consists of 8 gate chains with a total of 1680 Boost gates comprising AND, OR, XOR and INV. The logic gates and clock generator occupy a total area of 315×320µm 2 . Complementary resonant clocks φ and φ are generated with an Hbridge topology. Pulses a and b at 180˚ are derived from a reference clock and drive the clock generator switches in tandem, periodically replenishing dissipated energy in the system. The frequency f of the reference clock is programmable in the range 700MHz ≤ f ≤ 1.3GHz.The resonant clocks oscillate at the reference frequency f. For efficient operation, f should be near the natural frequency where C is the total capacitance resonated with inductance L. To explore the impact of design trade-offs on energy efficiency, the clock generator is designed with prog...

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A GHz-class charge recovery logic

Cited by 3 publications

References 3 publications

Cascadable adiabatic logic circuits for low-power applications

Cascadable adiabatic logic circuits for low-power applications

Power optimization for VLSI circuits and systems

A 1.1ghz charge-recovery logic

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