A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

Chen, C.; Wallangen, V.; Gong, D. T.; Grace, C.; Sun, Quan; Guo, D.; Kulis, Szymon; Leroux, Paul; Liu, C.; Liu, T.; Moreira, P.; Prinzie, Jeffrey; Xiao, Le; Ye, J.

doi:10.1088/1748-0221/14/07/c07005

Cited by 8 publications

(7 citation statements)

References 6 publications

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“…Third, it complies with space constraints, and thermal management and grounding and shielding requirements, including the independent biasing of separate serial powering chains on the detector. The ASICs for the opto-electrical conversion are located on the Optoboard (Figure 3): each Optoboard hosts four GigaBit Cable Receiver (GBCR) chips [4], four low-power GigaBit Transceiver (lpGBT) chips [5], a Versatile Link Transceiver Plus (VTRx+) module [6] and a bPOL2V5 DC/DC converter [7].…”

Section: The Itk Pixel Data Transmission Chain and The Optosystemmentioning

confidence: 99%

The Opto-electrical conversion system for the data transmission chain of the ATLAS ITk Pixel detector upgrade for the HL-LHC

Franconi¹

2022

J. Phys.: Conf. Ser.

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The future High-Luminosity era of the Large Hadron Collider, with its unprecedented instantaneous luminosity, will impose new challenges on the LHC experiments. ATLAS will replace its inner detector with a new all-silicon Inner Tracker (ITk), whose innermost layers will be based on pixel technology and are expected to produce a data output of about 11 Tb/s. A high-speed transmission chain with many parallel lines running at 1.28 Gb/s will transmit data from the detector to an opto-electrical conversion system. This Optosystem features custom-designed radiation-hard electronics devoted to signal equalisation, aggregation (to 10.24 Gb/s) and optical-electrical conversion.

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Section: The Itk Pixel Data Transmission Chain and The Optosystemmentioning

confidence: 99%

The Opto-electrical conversion system for the data transmission chain of the ATLAS ITk Pixel detector upgrade for the HL-LHC

Franconi¹

2022

J. Phys.: Conf. Ser.

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“…Development and evaluation of prototypes for the ATLAS ITk pixel detector Opto Board the signal is serialized, equalized and converted from an electrical to an optical signal. These operations are performed by three application specific integrated circuits, the lpGBT [8], the GBCR [9] and the VTRX+ [10], respectively. The optical signal is then sent at 10.24 Gbps via a 65 m long fibre trunk to the readout server, which uses the FELIX system [11].…”

Section: Pos(ichep2022)1016mentioning

confidence: 99%

Development and evaluation of prototypes for the ATLAS ITk pixel detector

Moser¹

2022

Proceedings of 41st International Conference on High Energy Physics — PoS(ICHEP2022)

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In light of the high-luminosity upgrade of the LHC at the end of this decade, the ATLAS experiment will replace its current inner detector by an all-silicon tracker, the ITk. The ITk will outperform the current tracker not only in terms of granularity and radiation hardness, it will also significantly reduce the material budget. To demonstrate that large scale detectors can be built following the envisioned ITk design, smaller scale prototypes are constructed for each of the ITk sub-systems. Three prototypes are built from silicon pixel modules, mimicking the structures in the innermost ITk layers. They provide the unique opportunity to evaluate aspects like the mechanical integration, the serial powering and cooling of modules, as well as the data acquisition in a realistic environment.

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“…If a 256×256 pixel array running at a 1 MHz frame rate is assumed and if each pixel has a 12-bit ADC with 2 gain bits, the uncompressed transmission bitrate would be 917 Gbps. Individual high-speed transmitters in 65 nm CMOS have been demonstrated at 5-10 Gbps [23,24] and the Timepix4 ASIC is designed with 16 × 10.24 = 164 Gbps off-chip bandwidth [25]. At these extreme bit-rates the number of transmitters needed to send uncompressed data would make a 1 MHz frame rate out of the question.…”

Section: Outlook and Conclusionmentioning

confidence: 99%

Strategies for on-chip digital data compression for X-ray pixel detectors

Hammer¹,

Yoshii²,

Miceli³

2021

J. Inst.

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The continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of > 1.5× independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of > 4×, > 7×, and > 8× for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12×.

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A gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

Cited by 8 publications

References 6 publications

The Opto-electrical conversion system for the data transmission chain of the ATLAS ITk Pixel detector upgrade for the HL-LHC

The Opto-electrical conversion system for the data transmission chain of the ATLAS ITk Pixel detector upgrade for the HL-LHC

Development and evaluation of prototypes for the ATLAS ITk pixel detector

Strategies for on-chip digital data compression for X-ray pixel detectors

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