A global BIST methodology

Abstract

This paper presents a BIST methodology for CMOSgate-arrays. This BIST method involves the extension of a design-independent embedded grid-based test technology that is provided in the base of the gate array to provide an automatic and complete serf-test. The use of globally shared test electronics minimizes the area overhead required, while the massive observability of internal circuit nodes afforded by an embedded grid allows high fault coverage of both stuck-at and manufacturing defects, such as shorts and opens, to be achieved.

Self-Programmable Shared BIST for Testing Multiple Memories

“…The worst memory cut in terms of delay from & to BIST is highlighted in the figure 8. In order to test memory M1 at speed i.e 1.23 ns (access time of M1), the BIST must run at a faster speed and it is apparent from the floorplan that it is not possible to achieve that frequency for a shared BIST without inserting the pipeline flops.…”

“…The wrappers include a data decoder block, cut selection decoder, output compacter and transparent mode multiplexers. The conventional wrappers as proposed in other schemes [6][7][8][9][10][11][12][13] are in itself a programmable BIST, capable of decoding the micro-codes and generating the memory patterns and data comparison, leading to high area of wrapper. The proposed BIST controller is a shared central block and is designed for generating the operations according to a pre-defined or silicon programmable algorithm.…”

“…Recently, split architectures for shared memory BIST have been proposed [6][7][8][9][10][11][12][13]. The test algorithm and memory information is stored centrally in a shared engine.…”

Test cycle count reduction in a parallel scan BIST environment

“…In this paper we address test cycle count reduction in a "circular" BIST environment in which a centralized LFSR is used to generate test patterns and compress test responses [9] and in which an address counter together with address decoding logic is used to address "words" of scannable storage elements arranged in a R A M like structure.The basic structure of the BIST scheme analyzed in this paper is shown in Figure 1. As in [ 11, we assume a parallel access scan environment, i.e the sequential elements can be assigned values or read using a parallel access mechanism in which the sequential elements are accessed using address and data lines.…”

“…Thus, in addition to test-points in storage elements it is possible to add a large number of additional test-points, each of which consists of a single transistor at low cost. These test-point transistors can be used to provide massive observability of internal circuit nodes so significantly increasing the fault coverage achievable [9],[ 12-131. Another alternative to adding testpoints is to use Iddq testing.…”