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This paper discusses delay fault test generation methodologies that avoid the area and performance overhead of enhanced scan elements by the use of scan and functional justification techniques. Issues with the use of scan justification and functional justification in a standard edge-triggered single clock scan environment are discussed. A functional justification based path delay test generator for circuits designed using standard scan elements is described. This test generator uses a calculus that allows circuits containing internal tri-state elements and bi-directional ports to be supported. Clock suppression techniques are employed to minimize state justification requirements. INTRODUCTIONRecently, test generation for delay faults, which are faults that cause an increase in the delays of circuit paths, has been the subject of extensive investigations [1-271. To apply delay test patterns in a scan-design, a special-purpose scan-element with an extra holding latch has usually been required. Most of the research on delay test generation has assumed the use of these special scan elements that have been enhanced so that they can store two states. However, delay testing based on such scan elements has seen only limited use because of the area and performance overhead incurred. Recently, to avoid the overhead of special purpose scam

This paper presents a BIST methodology for CMOSgate-arrays. This BIST method involves the extension of a design-independent embedded grid-based test technology that is provided in the base of the gate array to provide an automatic and complete serf-test. The use of globally shared test electronics minimizes the area overhead required, while the massive observability of internal circuit nodes afforded by an embedded grid allows high fault coverage of both stuck-at and manufacturing defects, such as shorts and opens, to be achieved.

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