A unifying methodology for intellectual property and custom logic testing

Bhatia, S.; Gheewala, T.; Varma, P.

doi:10.1109/test.1996.557121

Cited by 40 publications

(16 citation statements)

References 14 publications

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“…Performance degradation of this technique can be severe depending on the number of scanned core I/Os. In [4], the utilization of a new type of storage element is proposed for the core outputs; both the observation of the core responses and the justification of the stimuli for testing the neighboring core(s) can be performed at significantly reduced performance cost. However, the technique still suffers from performance degradation due to the multiplexer insertion at the core inputs.…”

Section: Previous Workmentioning

confidence: 99%

A Non-Intrusive Isolation Approach for Soft Cores

Sinanoglu

Петров

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Cost effective SOC test strongly hinges on parallel, independent test of SOC cores, which can only be ensured through proper core isolation techniques. While a core isolation mechanism can provide controllability and observability at the core I/O interface, its implementation may have various implications on area, functional timing, test time and data volume, and at-speed coverage on the core interface. In this paper, we propose a non-intrusive core isolation technique that is based on the utilization of existing core registers for isolating the core. We provide a core register partitioning algorithm that is capable of identifying the core interface registers, and of robustly isolating a core, resulting in a computationally efficient core isolation implementation that is area and performance efficient at the same time. The proposed isolation technique also ensures minimal test time increase and no at-speed coverage loss on the core interface, offering an elegant solution for soft cores, and thus enabling significant SOC test cost reductions.

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Section: Previous Workmentioning

confidence: 99%

A Non-Intrusive Isolation Approach for Soft Cores

Sinanoglu

Петров

2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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show abstract

“…Performance degradation of this technique can be severe depending on the number of scanned core I/Os. In [3], the utilization of a new type of storage element is proposed for the core outputs; both the observation of the core responses and the justification of the stimuli for testing the neighboring core(s) can be performed at significantly reduced performance cost. However, the technique still suffers from performance degradation due to the multiplexer insertion at the core inputs.…”

Section: Previous Workmentioning

confidence: 99%

Partial core encryption for performance-efficient test of SOCs

Sinanoglu¹,

Orailoglu²

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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The isolation of a core through full I/O scan helps ease SOC test challenges; yet the performance of high-speed SOCs is significantly hampered. We propose a partial core encryption methodology wherein the core vendor unveils only a small part of the core logic, successfully satisfying core IP protection requirements. Once the partially encrypted cores are merged into an SOC, the system integrator performs test generation on the visible SOC logic only, greatly reducing the test generation effort expended. By utilizing the test data provided by the core vendor as well, the SOC integrator can test the SOC with no performance degradation. We present an efficient fault analysis based core encryption algorithm which is guided by judiciously computed testability measures. The experimental results confirm the significantly high encryption levels attained by the proposed encryption algorithm.

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“…TAMs and wrappers are important components of existing SoC test architectures; TAMs deliver test sequences to cores while test wrappers translate these test sequences into vectors that can be applied directly to cores. There exist several TAM architectures, such as the test bus [2], the test rail [3], and multiplexed access [4]. Wider TAMs allow better test access at the expense of wiring area overhead.…”

Section: Introductionmentioning

confidence: 99%