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This paper describes the first behavioral synthesis system that incorporates a hierarchical test generation approach to synthesize area-efficient and highly testable controller/data path circuits. Functional information of circuit modules is used during the synthesis process to facilitate complete and easy testability of the data path. The controller behavior is taken into account while targeting data path testability. No direct controllability of the controller outputs through scan or otherwise is assumed. The test set for the combined controller/data path is generated during synthesis in a very short time. Near 100% testability of combined controller and data path is achieved. The synthesis system easily handles large bit-width data path circuits with sequential loops and conditional branches in their behavioral specification, and scheduling constructs like multicycling, chaining and structural pipelining. An improvement of about three to four orders of magnitude was usually obtained in the test generation time for the synthesized benchmarks as compared to an efficient gate-level sequential test generator. The testability overheads are almost zero. Furthermore, in many cases at-speed testing is also possible.Index Terms-Controller/data path testing, hierarchical testability, high-level synthesis, synthesis for testability.

Testing of sequential circuits i s greatly facilitated by using scan techniques t o directly control and observe the latches. Adding scan capability after logic synthesis m a y incur significant area and delay overheads. For such cases, we present a technique called synthesis f o r parallel partial scan in which latches are incrementally selected f o r partial scan based o n some new structural analysis criteria that we introduce. Delay overhead i s minimized, in m o s t cases m a d e zero or nearly zero, by judiciously selecting the latches an the non-critical paths. A heuristic i s used t o maximally merge the scan logic with the combinational logic of the sequential circuit to minimize the area overhead. T h e latches used in our scheme are normal, non-scan latches. Ezperimental results o n ISCAS '89 benchmarks resynthesized by our method indicate that w e can, in general, achieve the same level of testability with f e w e r latches selected f o r partial scan, as compared t o preuious methods based o n structural analysis.