Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches

Bhatia, S.; Jha, Niraj K.

doi:10.1109/iccd.1994.331862

Cited by 32 publications

(17 citation statements)

References 18 publications

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“…The verifiability V of a TCDF variable is the ability to verify its value by either controlling or observing it. Controllability, observability and verifiability are all Boolean parameters and only take the values of 1 or 0, depending on whether the variable has the corresponding ability or not [10]. Next, we add another field to these parameters, which designates the cycle when the particular property of a variable is desired.…”

Section: Test Environment Generationmentioning

confidence: 99%

“…Figure 1 shows the RTL circuit of benchmark Tseng taken from [13]. This particular RTL implementation was synthesized by the Genesis high-level synthesis system [10]. The shaded test multiplexer is not a part of the original circuit and will be discussed later.…”

Section: Making Rtl Modules Random-pattern Testablementioning

confidence: 99%

“…It consists of operations mapped to modules in the circuit and variables mapped to registers. The TCDF is used along with the functional information of modules to obtain a set of justification and propagation paths called test environments for some operations/variables in them [10]. The test environment of an operation (variable) guarantees the existence of a test path from the primary input ports of the circuit to the inputs of the module (register) to which the operation (variable) is mapped and a path from the output of the module (register) to a primary output port of the circuit.…”

Section: Introductionmentioning

confidence: 99%

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A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Ghosh

Jha

Bhawmik³

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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This paper introduces a novel scheme for testing register-transfer level controller/data paths using built-in self-test (BIST). The scheme uses the controller netlist and the data path of a circuit to extract a test control/data flow (TCDF) which consists of operations mapped to modules in the circuit and variables mapped to registers. This TCDF is used to derive a set of symbolic justification and propagation paths (known as test environment) to test some of the operations and variables present in it. If it becomes difficult to generate such test environments with the derived TCDFs, a few test multiplexers are added at suitable points in the circuit to increase its controllability and observability. This test environment can then be used to exercise a module or register in the circuit with pseudorandom pattern generators which are placed only at the primary inputs of the circuit. The test responses can be analyzed with signature analyzers which are only placed at the primary outputs of the circuit. Every module in the module library is made randompattern testable, whenever possible, using gate-level testability insertion techniques. Finally, a BIST controller is synthesized to provide the necessary control signals to form the different test environments during testing, and a BIST architecture is superimposed on the circuit. Experimental results on a number of industrial and university benchmarks show that high fault coverage (>99%) can be obtained with our scheme in a small number of test cycles at an average area (delay) overhead of only 6.4% (2.5%).

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Section: Test Environment Generationmentioning

confidence: 99%

Section: Making Rtl Modules Random-pattern Testablementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Ghosh

Jha

Bhawmik³

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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“…Instead, datapath and controller are tested separately in different test sessions. The basic test scheme is similar to what [5] proposed. That is the controller output signals are multiplexed with some or all of the datapath primary outputs, thus, making them directly observable.…”

mentioning

confidence: 97%

Detecting undetectable controller faults using power analysis

Carletta¹,

Papachristou²,

Nourani³

Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)

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In systems consisting of interacting datapaths and controllers, the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This is not possible when the controller-datapath pair is an embedded system designed as a hard core. This work facilitates the testing of controller-datapath pairs in a truly integrated fashion.The key to the approach is a careful examination of the types of gate level stuck-at faults that can occur within the controller. A class of faults that are undetectable in an integrated test by traditional means is identified. These faults create faulty but functional circuits. The effect of these faults on power consumption is explored, and a method based on power analysis is given for detecting these faults. Analysis is given for three example systems. ½ ÁÒØÖÓ Ù Ø ÓÒThis work addresses the problem of testing systems that consist of interacting datapaths and controllers, and facilitates the testing of these controller-datapath pairs in an integrated fashion. Typically, testing of datapaths and controllers is done independently, rather than as two parts of an inseparable pair. However, the separation may not be feasible in embedded system designs where the controller-datapath is a reusable component or core to be integrated in a system-on-chip. Separate testing does not adequately cover the interface between the controller and the datapath.Few, if any, design tools address the issue of how to test datapath and controller in an integrated way. The main difficulty in integrated testing is the need to propagate controller faults through the datapath for observation at the datapath outputs. In their work on integrating controller and datapath test, Dey et. al. observed that even when the controller and datapath are 100% testable separately, the combination of them has usually much lower coverage. This degradation, in their opinion, occurs due to the correlation and dependency between the control signals[8].In our recent work [16] we addressed the problem of integrated test, and provided a test synthesis method to allow the controller to be easily tested as part of the integrated system. However, our method required design-for-testability insertion at the controllerdatapath interface, and therefore is not appropriate for embedded cores. In our work we came across a new type of system-level redundant fault, originating in the controller, that while having no functional effect yet produces an undesirable power increase during normal system operation. This issue has been the motivation and focus of our present work. The key to our approach is a careful analysis of the system-functionally redundant faults, which are undetectable in any traditional test that treats the pair as an integrated system. What we found is that many of these faults have a significant, measurable effect on dynamic power consumption. We remark here that these faults can not be caught by IDDQ techniques [1], which measure quiescent current. TX 75083.To the...

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“…The set of value ranges of a component SSA variable{Wi[Li : Ui : O]},where i = 1,2,3 .... n a. Simple Assignments: A simple assignment that occurs outside a loop could be in a basic block that either does or.…”

mentioning

confidence: 99%

An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques

Seshadri

Hsiao

International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034)

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This research applies formal dataflow analysis and techniques to high-fevel DFT. Our proposed approach improves testability of the behavioral-level circuit description {such as in VHDL) F e d on propagation of the value ranges of variables throtigh the circuit's Control-Data Flow Graph {CDFG). The resulting testable circuit is accomplished via controllability land observability computations from these value ranges dnd insertion of appropriate testability enhancements, while keeping the design area-performance overhead to a hinimum. I IntrodJctionTraditionally, P S I design and test processes have been kept separate, ;with test considered only at the end of the design cycle. However, in contemporary design flows, test merges with design much earlier in the process, creating a design-for-test\(DFT) process flow, the goal of which is to produce hierarFhically testable designs. A design is said to be hierarchically testable, if the input (output) ports of every module in Ithe design hierarchy, are easily controllable (observable) through system inputs (outputs) [I].Classical DFT strategies have been conventionally limited to the end of the design phase, when a detailed gatelevel description of the design is available [6, 7, 81. Testability featured that are incorporated into the design at the post-synthesis step result in area and delay penalties. These stTuctural testability enhancement techniques fall into the following categories: Built-in self-test (BIST), non-scan and (scan-based DFT. In general, the amount of scan required to get an acceptable fault coverage varies from design t? design. At-speed testing of a circuit is not possible whenlscan tests are used, due to scanning in and out of flip-flopI values.Recent studies [l, 2, 3, 4, 5, 13, 151 have shown that if testability is not addressed during behavioral synthesis, many modules and registers in the resultant registertransfer-level CRTL) circuit may not be testable for the operations and/or variables mapped to them. The problem is exacerbated in the presence of loops, constants and ret convergent fanout in the control-data flow graph (CDFG) corresponding1 to the design.In [9], the' authors proposed a partial-scan selection I mechanism that works on the CDFG of a design derived I I I I I I I l from its behavioral description. Hard-to-test areas of the design are identified by the evaluated controllability and observability measures, and test point insertion techniques such as those described in [5] are applied. Lastly, flip-flops corresponding to variables that are hard to control and observe are selected for partial-scan to maximize the impact on testability of the design. The controllability measures obtained in this fashion, however, do not consider the value ranges of the variables and the probabilities of propagating these value ranges to the nodes in the CDFG. In [17], the authors propose a behavioral testability enhancement technique based on the analysis of values and variable probabilities obtained from profiling of the high-level description. The si...

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Behavioral synthesis for hierarchical testability of controller/data path circuits with conditional branches

Cited by 32 publications

References 18 publications

A BIST scheme for RTL controller-data paths based on symbolic testability analysis

A BIST scheme for RTL controller-data paths based on symbolic testability analysis

Detecting undetectable controller faults using power analysis

An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques

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